• Korean Journal of Computational Design and Engineering
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• v.12 no.2
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• pp.87-94
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• 2007

The functional behavior of a consumer electronic product is nearly all expressed with human-machine interaction (HMI) tasks. Although physical prototyping and computer aided design (CAD) software can show the appearance of the product, they cannot properly reflect its functional behavior. In this paper, we propose an approach to virtual prototyping (VP) that incorporates HMI functional simulation into virtual reality techniques in order to enables users to capture not only the realistic look of a consumer electronic product but also its functional behavior. We adopt state transition methodology to capture the HMI functional behavior of the product into a state transition chart, which is later used to construct a finite state machine (FSM) for the functional simulation of the product. The FSM plays an important role to control the transition between states of the product. We have developed a VP system based on the proposed approach. The system receives input events such as mouse clicks on buttons and switches of the virtual prototype model, and it reacts to the events based on the FSM by activating associated activities. The system provides the realistic visualization of the product and the vivid simulation of its functional behavior using head-mounted displays (HMD) and stereo speakers. It can easily allow users to perform functional evaluation and usability testing. A case study about the virtual prototyping of an MP3 player is given to show the usefulness of the proposed approach.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.6
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• pp.470-477
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• 2015

This paper presents a new technique for generating an optimum synchronizable test sequence that can be applied in the distributed test architecture where both external synchronization and input/output operation costs are taken into consideration. The method defines a set of phases that constructs a tester-related digraph from a given finite state machine representation of a protocol specification such that a minimum cost tour of the digraph with intrinsically synchronizable transfer sequences can be used to generate an optimum synchronizable test sequence using synchronizable state identification sequences as the state recognition sequence for each state of the given finite state machine. This hybrid approach with a heuristic and optimization technique provides a simple and elegant solution to the synchronization problem that arises during the application of a predetermined test sequence in some protocol test architectures that utilize remote testers.

• Journal of KIISE:Software and Applications
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• v.30 no.7_8
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• pp.642-648
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• 2003

In this paper, we are interested in checking equivalence of FSMs(finite state machines). Two FSMs are equivalent if and only if their responses are always equal with each other with respect to the same external stimuli. Equivalence checking FSMs makes complicated FSM be substituted for simpler one, if they are equivalent. We can also determine the system satisfies the requirements, if they are all written in FSMs. In this paper, we regard equivalence checking problem as model checking one. For doing so, we construct the product model $M ={M_A} {\beta}{M_B} from two FSMs ${M_A} and {M_B}$. And we also get the temporal logic formula ${\Phi}$ from the equivalence checking definition. Then, we can check with model checker whether if satisfies ${\Phi}$, written $M= {.\Phi}$. Two FSMs are equivalent, if $M= {.\Phi}$ Otherwise, it is not equivalent. In that case, model checker generates counterexamples which explain why FSMs are not equivalent. In summary, we solve the equivalence checking problem with model checking techniques. As a result of applying to several examples, we have many satisfiable results.

• The KIPS Transactions:PartD
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• v.12D no.6 s.102
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• pp.863-868
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• 2005

Hardware and software codesign framework called PeaCE(Ptolemy extension as a Codesign Environment) was developed. It allows to express both data flow and control flow which is described as fFSM which extends traditional finite state machine. While the fFSM model provides lots of syntactic constructs for describing control flow, it has a lack of their formality and then difficulties in verifying the specification. In order to define the formal semantics of the fFSM, in this paper, firstly the hierarchical structure in the model is flattened and then the step semantics is defined. As a result, some important bugs such as race condition, ambiguous transition, and circulartransition can be formally detected in the model.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.583-584
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• 2009

This paper provides a method to analyze the dynamical system. It considers the fact of realistic delay in dynamical system analysis for the first time. The method uses timeline and state space to emulate the inhibitive coupling nodes evolving procedure in transmission delayed environment. The resultant finite state machine shows the system predictability and hardware implementation feasibility.

• Journal of KIISE:Software and Applications
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• v.28 no.9
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• pp.634-648
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• 2001

Message Sequence Charts(MSC) has been used to describe the interactions of numerous concurrent tasks in telecommunication software. After the MSC specification is verified in requirement analysis phase, it can be used not only to synthesize state-based design models, but also to generate test sequences. Until now, the verification is accomplished by generating global state transition graph using the location information only. In this paper, we extend the condition statement of MSC to describe the activation condition of scenarios and the change of state variables, and propose an approach to construct global finite state machine (GFSM) using this information. The GFSM only includes feasible states and transitions of the system. We can generate the test sequences using the existing FSM-based test sequence generation technology.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.2
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• pp.193-199
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• 2014

In this paper, we present an overview of the structure of a lab-built powered knee prosthesis and the control of it. We build a powered prosthesis prototype on the basis of previous researches and aim at obtaining the essential technology related with its control. We adopt the slider-crank mechanism with a DC motor as an actuator to manipulate the knee joint. We also build an embedded control system for the prosthesis with a 32-bit DSP controller as a main computation unit. We divide the gait phase into five stages and use a FSM (Finite State Machine) to generate a torque reference needed for each stage. We also propose to use a position-based impedance controller for driving the powered knee prosthesis stably. We perform some walking experiments at fixed speeds on a tread mill in order to show the feature of the built powered prosthesis. The experimental results show that our prosthesis has the ability to provide a functional gait that is representative of normal gait biomechanics.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2004.05a
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• pp.607-610
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• 2004

It is still not sufficient for the famous embedded software test methods such as Finite State Machine, Software Cost Reduction and model coverage based test case generation, to pinpoint where bugs hang around and to figure out what makes the bugs. A new approach to ameliorate the drawbacks is proposed in this paper. In the approach, we define a generic model for embedded software. And we also define failure mechanism for embedded software, and a way to generate test cases based on it.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1567-1576
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• 2018

The reliability of grid-connected inverters can be improved by algorithms capable of diagnosing faults in LCL filters. A fault diagnostic method during inverter startup is proposed. The proposed method can accurately generate and monitor information on the peak value and the location of the peak frequency component of the step response of a damped LCL filter. To identify faults, the proposed method compares the evaluated response with the response of a healthy higher-order damped LCL filter. The frequency components in the filter voltage response are first analytically obtained in closed form, which yields the expected trends for the filter faults. In the converter controller, the frequency components in the filter voltage response are computed using an appropriately designed fast Fourier transform and compared with healthy LCL response parameters using a finite state machine, which is used to sequence the proposed startup diagnostics. The performance of the proposed method is validated by comparing analytical results with the simulation and experimental results for a three-phase grid-connected inverter with a damped LCL filter.

• Journal of the Korea Computer Graphics Society
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• v.14 no.2
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• pp.1-8
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• 2008

This paper presents a design of a situation training system supporting mixed-reality for the developmental disabled. The training scenario is developed for the disabled to improve the sense of sight and perception. The user sticks a virtual pin into a hole in the working board according to the direction and the appropriate feedback is delivered based on the FSM(Finite State Machine). In order to improve the reality and the training effect, the user's hand is inserted in the virtual training environments and the tactile sensation is provided using the haptic device.