• 제목/요약/키워드: Finite wordlength effects

검색결과 7건 처리시간 0.021초

디지털 PID 제어기의 제한 요소 영향 분석(II):유한 단어 길이 문 (Analysis of Limitation Factor Effects on Digital PID Controller(II) : Finite Wordlength Issue)

  • 홍석민;김인중;이상정
    • 대한전기학회논문지
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    • 제43권2호
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    • pp.318-329
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    • 1994
  • This paper deals with the finite wordlength effect on the performance of digital PID controllers. The finite wordlength, one of the major limitation factors in digital controllers, results on two kinds of quantization error : the signal quantization error and the coefficient quantization error. This paper derives the variance of the plant output due to the signal quantization error. Using stability margins as performance criterion, the statistical wordlength concept is adopted for coefficient wordlength selection. Finally, the experimental results exhibit satisfactory performance of the digital PID controller with statistical coefficient wordlength.

$\delta$ 변환을 채택한 디지틀 PID 제어기 설계 (Digital PID controller design adopting the delta transforms)

  • 김인중;홍석민;이상정
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 19-21 Oct. 1992
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    • pp.981-986
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    • 1992
  • In order to implement the digital PID control algorithm, it is necessary to consider the effect of the finite word length(FWL). In this paper, we show the FWL effect in the digital PID controllers. The conception analyse the effects of the signal quantization error in the digital PID algorithm and the coefficient wordlength determined from performance criteria with the statistical wordlength concept. Throughout this paper, it is dealt with the type of controller structure based delta operator the delta operator has such advantages are superior rounfoff noise perfoff noise performance, more accurate coefficient repersentation, and less sensitive control law.

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FS-CELP 음성 부호화기의 고정 소수점 성능 분석 및 구현 (Fixed-point performance analysis and implementation of the FS-CELP vocoder)

  • 손종서;김시현;강지양;성원용
    • 한국통신학회논문지
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    • 제21권2호
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    • pp.365-374
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    • 1996
  • Finite wordlength effects of the FS-1016 CELP(Code Excite Linear Prediction) vocoder algorithm) is analyzed, and a block floating-Point implementation method is employed to improve the fixed-point performance. An efficient run-time integer wordlength estimation algorithm is developed, and the overall system performance. An efficient run-time integer wordlength estimation algorithm is developed, and the overall system performance is verified in real-time using a TMS320C50 emulation board. Autoscaler software that conducts simulation-based automatic scaling to provide a floating-point like programming environment is used for this application development.

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Sliding-DFT를 이용한 다채널 위상 측정 FPGA 시스템 (Sliding-DFT based multi-channel phase measurement FPGA system)

  • 어진우;장태규
    • 전기전자학회논문지
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    • 제8권1호
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    • pp.128-135
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    • 2004
  • 본 논문에서는 sliding-DFT에 순환 구현에 기반한 위상 측정 앨고리즘을 제안하였다. 제안한 앨고리즘은 주파수 변이, 누적 잡음, 계수 근사 영향 등의 오차영향에 강인한 특성을 가지도록 설계되었다. DFT 계수의 유한 비트 근사 구현에 의한 위상 오차는 크기 오차에 비해 매우 작게 나타난다. 위상 오차의 혁신적인 감소는 근사 계수가 복소평면 상에서 4사분면상에 대칭적으로 존재함을 이용하여 얻을 수 있다. 제안한 앨고리즘을 시분할 공유 구조에 기반한 4-채널 전력선 위상 측정 시스템을 설계하고 구현하였다. 구현한 시스템의 동작은 실시간으로 host processor 시스템과 다채널 함수 발생기를 통한 test 환경에서 실험적으로 확인하였다. 제안한 앨고리즘의 위상 측정에 있어 정확한 특성과 유한비트 근사 영향에 강인한 특성은 특히, 빠른 처리 속도와 구현의 감소함이 주요 설계 고려사항인 ASIC 이나 microprocessor에 기반의 임베디드 시스템 적용에 중대한 효과를 제공할 수 있을 것이다.

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디지털 제어기 구현시 FWL 영향에 대한 안정도 여유 (Stability Margin of Finite Wordlength(FWL) Effects in Digital Implementation of Controllers)

  • 김진호;최선욱;김영철
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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    • pp.533-536
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    • 1999
  • We consider digital implementation problems of continuous-time controllers. In general, digital controllers use fixed point representation of number and of finite word length(FWL). Under these conditions, this paper investigates the closed-loop stability caused by three design constraints; (i) finite precision representation of the controller parameters, (ii) realization forms such as direct form, cascade form, and parallel form, and (iii) sampling time. We calculate the coefficient stability margins of both predesigned controllers and controller to be implemented. This method can be applied to determine the word length, realization structure, and sampling time so that remains the stability.

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DFT 연산 FPGA 모들에 기반한 위상 측정 앨고리즘의 구현 (FPGA Implementation of Recursive DFT based Phase Measurement Algorithm)

  • 안병선;김병일;장태규
    • 대한전기학회논문지:시스템및제어부문D
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    • 제54권3호
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    • pp.191-193
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    • 2005
  • This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The proposed algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

양자화와 오버플로우 비선형성을 가지는 이산시간 폴리토픽 불확실 지연 시스템의 강인 안정성 (Robust Stability for Discrete-time Polytopic Uncertain Delay Systems with Quantization/overflow Nonlinearities)

  • 김종해
    • 전기학회논문지
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    • 제61권12호
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    • pp.1898-1902
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    • 2012
  • In this paper, we consider the delay-dependent robust stability condition for polytopic uncertain systems with interval time-varying delay using various combinations of quantization and overflow nonlinearities. A robust stability condition for uncertain systems with time-varying delay and quantization/overflow nonlinearities is proposed by LMI(linear matrix inequality) and Lyapunov technique. It is shown that the proposed method is less conservative compared to the recent results by numerical examples.