• Journal of the Korea Society of Computer and Information
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• 제25권11호
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• pp.59-65
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• 2020

Lately the VR (Virtual Reality) game genre is becoming increasingly more popular and it has been cementing its place in the market as its own independent game genre. The key advantage of VR is that it lowers the barrier between player and the virtual world, thus creating an immersive experience. The suggested method develops a game that allows the player to experience what it is like to be visually impaired using the unique characteristics of VR. A distinctive feature of this game is that the character is provided only a limited range of sight, which is created using silhouette outlines. This restrictive visual field is then grafted onto VR and the player can indirectly experience blindness in a highly immersive manner. The silhouette outline along with the particle system is created using Oculus Rift, a headset highly used in VR game development, and Unity 3D game engine. We will also explain in detail regarding the removal of borders between the objects.

• Journal of IKEEE
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• 제19권1호
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• pp.10-17
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• 2015

In this Paper, an efficient method of FPGA based design and implementation of Sobel Edge detector block using 3-Line buffers is presented. The FPGA provides the proper and sufficient hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipe-lined method is used to implement the edge detector. The proposed Sobel edge detection operator is an model using of Finite State Machine(FSM) which executes a matrix mask operation to determine the level of edge intensity through different of pixels on an image. This approach is useful to improve the system performance by taking advantage of efficient look up tables, flip-flop resources on target device. The proposed Sobel detector using 3-line buffers is synthesized with Xilinx ISE 14.2 and implemented on Virtex II xc2vp-30-7-FF896 FPGA device. Using matlab, we show better PSNR performance of proposed design in terms of 3-Line buffers utilization.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• 제12권6호
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• pp.597-604
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• 2019

In this paper, we propose an improved method on an adaptive application of the CPP(Chinese Postman Problem) algorithm to the protocol test suite generation for conformance testing. Also, we present an example application of this CPP algorithm to B-ISDN Q.2931 call/connection control procedure for the purpose of showing how it can be adapted to generate a test suite for conformance testing of a communication protocol. The proposed method has an advantage of an optimization technique which finds a minimum cost of test suite from a standardized specification, so this optimization technique of the CPP algorithm can be practically applied to a real environment for testing a conformity of a protocol implementation.

• Journal of Korea Game Society
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• 제16권6호
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• pp.79-90
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• 2016

Recently, many researchers have paid attention to the improved generation of AI agent in the area of game industry. Monte-Carlo Tree Search(MCTS) is one of the algorithms to search an optimal solution through random search with perfect information, and it is suitable for the purpose of calculating an approximate value to the solution of an equation which cannot be expressed explicitly. Games in Trading Card Game(TCG) genre such as the heartstone has imperfect information because the cards and play of an opponent are not predictable. In this study, MCTS is suggested in imperfect information card games so as to generate AI agents. In addition, the practicality of MCTS algorithm is verified by applying to heartstone game which is currently used.

• Journal of Advanced Navigation Technology
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• 제18권1호
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• pp.22-28
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• 2014

This paper presents the design and development of ECU simulator in order to verify automatic firmware update system of ECU SW on the vehicle. We designed and developed general-proposed ECU simulator as devide into HW and SW parts. HWadopt 32bit MPU, CAN, LIN, LCD, and touch-pad button to satisfy general-proposed ECU level. And SW constructed as finite-state-machine structure in order to support HW spec. We developed ECU manager which deliveries update data to verify validity of operation. And we tested ECU simulator with ECU manager. For test of validity of ECU simulator, we set 4 scenarios between ECU simulator and manager. As the result, we confirmed validity of operation in ECU simulator for automatic SW update system.

• International Journal of Automotive Technology
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• 제4권2호
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• pp.87-94
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• 2003

Recent advancements of permanent magnet (PM) materials and solid-state devices have contributed to a substantial performance improvement of permanent magnet machines. Owing to the rare-earth PMs, these motors have higher efficiency, power factor, output power per mass and volume, and better dynamic performance than induction motors without sacrificing reliability. Not surprisingly, they are continuously receiving serious considerations for a variety of automotive and propulsion applications. An electric vehicle (EV) requires a high-effficient propulsion system having a wide operating range and a capability of generating a high peak torque for short durations. The improvement of torque-speed performance for these systems is consequently very important, and researches in various aspects are therefore being actively pursued. A great emphasis has been placed on the efficiency and optimal utilization of PM machines. This requires attention to many aspects related to the machine design and overall performance. In this respect, the prediction of iron losses is particularly indispensable and challenging, especially for drives with a deep field-weakening range. The objective of this paper is to present iron loss estimations of a PM motor over a wide speed range. As aforementioned, in EV applications core losses can be significant during high-speed operation and it is imperative to evaluate these losses accurately and take them into consideration during the motor design stage. In this investigation, the losses are predicted by using an analytical model and a 2D time-stepped finite element method (FEM). The results from different analytical approaches are compared with the FEM computations. The validity of each model is then evaluated by these comparisons.

• Journal of the Institute of Convergence Signal Processing
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• 제9권3호
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• pp.201-207
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• 2008

This paper presents the implementation of a Tiling System about Preprocessing functions of JPEG 2000. The system covers the JPEG 2000 standard and is designed to determine the size of the image, to expand the image area and to split input image into several tiles. In order to split the input image with the progressive transmission into several tiles and transmit a tile of this image to others, this system store this image into Frame Memory. Therefore, this is designed as the Finite State Machine (FSM) to sequence through specific patterns of states in a predetermined sequential manner by using Verilog-HDL and be designed to handle a maximum 5M image. Moreover, for identifying image size for expansion, we propose several formula which are based on remainder after division (rem). we propose the true table which determines the size of the image input patterns by using results of these formula. Under the condition of TSMC 0.25um ASIC library, gate count is 18,725 and maximum data arrival time is 18.94 [ns].

• The Journal of Korean Institute of Communications and Information Sciences
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• 제33권6B호
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• pp.456-468
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• 2008

In this paper, we design Input/Output modules as a preference work for implementation of hybrid two stage AWG based WDM-PON and verify operations of each function modules through the logic simulation. This WDM-PON system provides service to 128 ONUs through 32 wavelength and one wavelength is shared for upstream transmission with four ONU while each wavelength is allocated to each ONU for downstream transmission. The designed WDM-PON MAC chip is based on sub-MAC which consists of one control unit and reception unit and four transmission unit. To design the reception and transmission unit of sub-MAC, we define the functions of the sub-MAC, pins of the modules, control signal and timing of each signal. We intend to design MAC chip with 1Gbps transmission rate. Thus the designed MAC chip is worked on 125MHz clock rate. We define FSM and design Input/Output modules with VHDL. The logic simulation of the modules is executed by the ModelSIM simulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제15권2호
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• pp.439-446
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• 2011

In this paper, we proposed and implemented a dedicated hardware for Huffman coding which is a method of entropy coding to use compressing multimedia data with video coding. The proposed Huffman codec consists Huffman encoder and decoder. The Huffman encoder converts symbols to Huffman codes using look-up table. The Huffman code which has a variable length is packetized to a data format with 32 bits in data packeting block and then sequentially output in unit of a frame. The Huffman decoder converts serial bitstream to original symbols without buffering using FSM(finite state machine) which has a tree structure. The proposed hardware has a flexible operational property to program encoding and decoding hardware, so it can operate various Huffman coding. The implemented hardware was implemented in Cyclone III FPGA of Altera Inc., and it uses 3725 LUTs in the operational frequency of 365MHz

• Journal of Welding and Joining
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• 제27권6호
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• pp.31-35
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• 2009

When conducting CTOD test, especially in thick welded steel plate, fatigue pre-cracking occasionally failed to satisfy the requirements of standards thus making the test result invalid. Internally accumulated residual stress of test piece has been thought as one of the main reasons. The propagation of fatigue crack, started from the tip of machined notch, which might have propagated irregularly due to residual stress field. To overcome this kind of difficulty three methods to modify the residual stress are suggested in standard i.e. local compression, reverse bending and stepwise high-R ratio method. In this paper not only multi pass welding but also local pre-compressing process of thick steel plate has been simulated using finite element method for clarifying variation of internal welding residual stress. The simulated results show that welding residual stress is compressive in the middle section of the model and it is predominantly increased after machining the specimen. Comparing as-welded state all component of the welding residual stress changing to compressive in the tip of machine notch whereas residual stress of the outer area remain as tensile condition relatively. Analysis results also show that this irregular residual stress distribution is improved to be more uniformly by applying local compression.