• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.381-384
• /
• 1999

In this paper, we addressed the problem of reducing the switching activity in pipeline datapath and proposed a solution. clock-gating method is a kind of practical technique for reducing switching activity in finite state machine. But, in the case that the target gated function unit has a pipeline structure, there is some spurious switching activity on each stage register group. This occur in early stage of every function enable cycle. In this paper we proposed a method to solve this problem. This method generates the enable signal to each pipeline stage to gate the clock feeding register group. Experimental results showed effective reduction of dynamic powers in pipeline circuits.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.4
• /
• pp.181-187
• /
• 2003

This paper presents an 125MHz, 128-phase phase-locked loop using interpolation technique for digital timing recovery. To reduce the power consumption and chip area, phase interpolation was performed over only selected windows, instead of overall period. Four clocks were used for phase interpolation to avoid the output jitter increase due to the interpolation clock (clock used for phase interpolation) switching. Also, the output clock was fed back to finite-state machine (FSM) where the multiplexer selection signals are generated to eliminate the possible output glitches. The PLL implemented in a $0.25\mu\textrm{m}$ CMOS process and dissipates 80mW at 2.5V supply and occupies $0.84\textrm{mm}^2.

• Journal of Korea Multimedia Society
• /
• v.8 no.9
• /
• pp.1269-1281
• /
• 2005

The control of character's behavior in games is determined by game designers. One of the popular method used in the control of character's behaviors is rule-based. The rule-based control of behavior makes the flow of play simple and boring. In this paper, we propose an efficient method of controling character's behaviors which can generate various actions of characters by using probability estimation applied to the character's behaviors.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2009.01a
• /
• pp.128-135
• /
• 2009

In this paper, we proposed an interactive GUI (Graphical User Interface) system to model buildings with an editable script. Our system also provides probabilistic finite-state machine (PFSM) to define the relationships of sub-models with transformation matrices and transition probabilities for constructing new novel building models automatically. User can not only get various building models by PFSM but also adjust the probabilities of sub-models from PFSM to get desired building models. As shown in the results, the various and vivid building models can be constructed easily and quickly for non-expert users. Besides, user can also edit the script file which is provided by our system to modify the properties directly.

• Proceedings of the Korean Information Science Society Conference
• /
• 2005.11b
• /
• pp.310-312
• /
• 2005

유한상태 기계는 신뢰성이 요구되는 내장형 시스템의 제어흐름을 표현하고 검증하는데 많이 사용되는 모델이다. 하지만 자체가 가지고 있는 단순함으로 인해 복잡한 시스템을 명세하기에는 부족하다. 이러한 유한상태 기계의 단점을 극복하기 위해 다양하게 확장시킨 유한상태 기계들이 나왔지만 이렇게 확장된 유한상태 기계들에 대한 정형 의미의 부재로 인해서 요구사항중 하나인 명세를 검증하는데 어려움이 따른다. 이에 우리는 확장된 유한상태 기계의 정형 단계 의미를 정의하고, 이를 사용하여 모델에 대한 정형검증을 수행하였다. 그 결과 레이스 조건(race condition)과 애매한 전이, 순환하는 전이 등의 버그들을 모델에서 정형적으로 검출 할 수 있었다.

• Proceedings of the KSR Conference
• /
• 2004.10a
• /
• pp.1241-1246
• /
• 2004

The verification confirms a correspondence between requirements and a specification before implementing. The problem in the formal method verifying a protocol specification using model checking is that the protocol behaviors must be always specified in L TS(Label Transition System). But if Region Automata is applied to the model checking, it is enable to verify whether properties are true on specification specified in I/O FSM(Input/Output Finite State Machine) as well as LTS. In this paper, we verify the correctness of rail signal control protocol type 1 specified in I/O FSM by using model checking method and region automata. This removes many errors and ambiguities of an informal method used in the past and saves down expenditures and times required in the protocol development. Therefore it is expected that there will be an increase in safety, reliability and efficiency in terms of the maintenance of the signaling system by using the proposed verification methods.

• ETRI Journal
• /
• v.19 no.4
• /
• pp.363-388
• /
• 1997

This paper describes a research result on automatic generation of abstract test cases from formal specifications by applying many related algorithms and techniques such as the testing framework, rural Chinese postman tour and unique input output sequence concepts. In addition, an efficient algorithm for verifying the strong connectivity of the reference finite state machine and the concept of unique event sequence are explained. We made use of several techniques to from an integrated framework for abstract test case generation from LOTOS and SDL specifications. A prototype of the proposed framework has been built with special attention to real protocol in order to generate the executable test cases in an automatic way. The abstract test cases in tree and tabular combined notation (TTCN) language will be applied to the TTCN compiler in order to obtain the executable test cases which re relevant to the industrial application.

• ETRI Journal
• /
• v.33 no.3
• /
• pp.466-469
• /
• 2011

As a fine-grained power gating method for achieving greater power savings, our approach takes advantage of the finite state machine with a datapath (FSMD) characteristic which shows sequential idleness among subcircuits. In an FSMD-based power gating, while only an active subcircuit is expected to be turned on, more subcircuits should be activated due to the power overhead. To reduce the number of missed opportunities for power savings, we deactivated some of the turned-on subcircuits by slowing the FSMD down and predicting its behavior. Our microprocessor experiments showed that the power savings are close to the upper bound.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.410-413
• /
• 2000

This paper suggests a methodology in which control signals for high-level synthesis are generated from SDL specification. SDL is based on EFSM(Extended Finite State Machine) model. Data path and control part are partitioned into representing data operations in the from of scheduled data flow graph and process behavior of an SDL code in forms of an abstract FSM. Resource allocation is performed based on the suggested architecture model and local control signals to drive allocated functional blocks are incorporated into an abstract FSM extracted from an SDL process specification. Data path and global controller acquired through suggested methodology are combined into structural VHDL representation and correctness of behavior for final circuit is verified through waveform simulation.

• Proceedings of the KIEE Conference
• /
• 2000.07b
• /
• pp.873-875
• /
• 2000

The self- and mutual- winding inductances can have an important influence on both the steady-state and transient dynamic performance of a machine. Especially, slotless topologics have inherently low self- and mutual-stator winding inductance. Thus, this paper describes an analytical model for predicting the winding inductance and results are compared to finite element analyses.