• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.925-927
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• 2005

The study is about a finite field multiplying unit, which performs a calculation t-times as fast as the Mastrovito's multiplier architecture, suggesting and using the 2-times faster multiplier architecture. Former studies on finite field multiplication architecture includes the serial multiplication architecture, the array multiplication architecture, and the hybrid finite field multiplication architecture. Mastrovito's serial multiplication architecture has been regarded as the basic architecture for the finite field multiplication, and in order to exploit parallelism, as much resources were expensed to get as much speed in the finite field array multipliers. The array multiplication architecture has weakness in terms of area/performance ratio. In 1999, Parr has proposed the hybrid multipcliation architecture adopting benefits from both architectures. In the hybrid multiplication architecture, the main hardware frame is based on the Mastrovito's serial multiplication architecture with smaller 2-dimensional array multipliers as processing elements, so that its calculation speed is fairly fast costing intermediate resources. However, as the order of the finite field, complex integers instead of prime integers should be used, which means it cannot be used in the high-security applications. In this paper, we propose a different approach to devise a finite field multiplication architecture using Mastrovito's concepts.

• 디지털산업정보학회논문지
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• 제16권2호
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• 디지털산업정보학회논문지
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• 제18권1호
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.935-938
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• 2003

The performance of elliptic curve based on public key cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. This work describes a finite field multiplier and divider which is implemented using SystemC. Also this present an efficient hardware for performing the elliptic curve point multiplication using the polynomial basis representation. In order to improve the speed of the multiplier with as a little extra hardware as possible, adopted hybrid finite field multiplication and finite field divider.

• 대한임베디드공학회논문지
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• 제14권6호
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• pp.313-319
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• 2019

Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.

• Journal of information and communication convergence engineering
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• 제12권3호
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• pp.145-153
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• 2014

The improvements of embedded processors make future technologies including wireless sensor network and internet of things feasible. These applications firstly gather information from target field through wireless network. However, this networking process is highly vulnerable to malicious attacks including eavesdropping and forgery. In order to ensure secure and robust networking, information should be kept in secret with cryptography. Well known approach is public key cryptography and this algorithm consists of finite field arithmetic. There are many works considering high speed finite field arithmetic. One of the famous approach is Montgomery multiplication. In this study, we investigated Montgomery multiplication for public key cryptography on embedded microprocessors. This paper includes helpful information on Montgomery multiplication implementation methods and techniques for various target devices including 8-bit and 16-bit microprocessors. Further, we expect that the results reported in this paper will become part of a reference book for advanced Montgomery multiplication methods for future researchers.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권5호
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• 대한전자공학회논문지SD
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• 제42권1호
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• pp.57-67
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• 2005

고속 스칼라곱 연산은 타원곡선 암호 응용을 위해서 매우 중요하다. 보안 상황에 따라 유한체의 크기를 변경하려면 타원곡선 암호 보조프로세서가 크기 가변 유한체 연산 장치를 제공하여야 한다. 크기 가변 유한체 연산기의 효율적인 연산 구조를 연구하기 위하여 전형적인 두 종류의 스칼라곱 연산 알고리즘을 FPGA로 구현하였다. Affine 좌표계 알고리즘은 나눗셈 연산기를 필요로 하며, projective 좌표계 알고리즘은 곱셈 연산기만 사용하나 중간 결과 저장을 위한 메모리가 더 많이 소요된다. 크기 가변 나눗셈 연산기는 각 비트마다 궤환 신호선을 추가하여야 하는 문제점이 있다. 본 논문에서는 이로 인한 클록 속도저하를 방지하는 간단한 방법을 제안하였다. Projective 좌표계 구현에서는 곱셈 연산으로 널리 사용되는 디지트 serial 곱셈구조를 사용하였다. 디지트 serial 곱셈기의 크기 가변 구현은 나눗셈의 경우보다 간단하다. 최대 256 비트 크기의 연산이 가능한 크기 가변 유한체 연산기를 이용한 암호 프로세서로 실험한 결과, affine 좌표계 알고리즘으로 스칼라곱 연산을 수행한 시간이 6.0 msec, projective 좌표계 알고리즘의 경우는 1.15 msec로 나타났다. 제안한 타원곡선 암호 프로세서를 구현함으로써, 하드웨어 구현의 경우에도 나눗셈 연산을 사용하지 않는 projective 좌표계 알고리즘이 속도 면에서 우수함을 보였다. 또한, 메모리의 논리회로에 대한 상대적인 면적 효율성이 두 알고리즘의 하드웨어 구현 면적 요구에 큰 영향을 미친다.

• 한국정보통신학회논문지
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• 제10권2호
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• pp.328-332
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• 2006

정보 보호 응용에 새로운 이슈가 되고 있는 ECC 공개키 암호 알고리즘은 유한체 차원에서의 효율적인 연산처리가 중요하다. 직렬 유한체 곱셈기의 근간은 Mastrovito의 직렬 곱셈기에서 유래한다. 본 논문에서는 polynomial basis 방식을 적용하고 식을 유도하여 Mastrovito의 직렬 유한체 곱셈방식의 3배 성능을 보이는 유한체 곱셈기를 제안하고, HDL로 기술하여 기능을 검증하고 성능을 평가한다. 설계된 3배속 직렬 유한체 곱셈기는 부분합을 생성하는 회로의 추가만으로 기존 직렬 곱셈기의 3배의 성능을 보여주었다. 비도 높은 암호용으로 연구된 유한체 곱셈 연산기는 크게 직렬 유한체 곱셈기, 배열 유한체 곱셈기, 하이브리드 유한체 곱셈기으로 분류되어 왔다. 본 논문에서는 Mastrovito의 곱셈기의 구조를 기본으로 하고, 수식적으로 공통인수를 끌어내어 후처리하는 기법을 유도하여 적용한다. 제안한 방식으로 설계한 새로운 유한체 곱셈기는 HDL로 구현하여 소프트웨어 측면 뿐 아니라 하드웨어 측면에서도 그 기능과 성능을 검증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.695-698
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• 2005

The finite-field multiplication can be applied to the wide range of applications, such as signal processing on communication, cryptography, etc. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cell, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-serial and digit-serial multipliers, the proposed multiplier shows relatively better performance with low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.