• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.2
• /
• pp.137-144
• /
• 2001

In this paper, a state assignment algorithm was proposed to reduce power consumption in control-flow oriented finite state machines. The Markov chain model is used to reduce the switching activities, which closely relate with dynamic power dissipation in VLSI circuits. Based on the Markov probabilistic description model of finite state machines, the hamming distance between the codes of neighbor states was minimized. To express the switching activities, the cost function, which also accounts for the structure of a machine, is used. The proposed state assignment algorithm is tested with Logic Synthesis Benchmarks, and reduced the cost up to 57.42% compared to the Lakshmikant's algorithm.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.2
• /
• pp.552-562
• /
• 1997

This paper proposes a formal method on confromance testing for INAP(AIN) test sequence generation by optimization technique.In order to implement and prove the dffectiveness of the proposed method,we specify the SRSM of INAP protocol SRF in SDL and generate I/O FSM by using our S/W tool. We generate an opti-mal test sequence by applying our method our method to this reference I/O FSM. We prove experimentally that the length of the generated test sequence by our method is more effective and shorter(i.e 32% improved)than the one geverated by UIO method,and estimate that The test coverage space of our test sequence is larger that of UIO method.

• Journal of information and communication convergence engineering
• /
• v.9 no.3
• /
• pp.305-309
• /
• 2011

This paper proposes a new rotational frequency detector (RFD) for phase-locked loop (PLL) or clock and data recovery (CDR) applications for fast frequency acquisition. The proposed RFD uses the four states finite state machine (FSM) model to accelerate the frequency acquisition time. It is modeled and simulated with MATLAB Simulink. The functionalities of the proposed RFD are examined and the results are compared to those of a conventional RFD. The proposed RFD's frequency acquisition time is four times faster than that of a conventional one. The proposed RFD incorporated with a phase detector (PD) in PLL or CDR is expected to improve the frequency and phase acquisition performance later greatly.

• Journal of Computing Science and Engineering
• /
• v.6 no.4
• /
• pp.257-266
• /
• 2012

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

• Journal of KIISE:Software and Applications
• /
• v.30 no.7_8
• /
• pp.642-648
• /
• 2003

In this paper, we are interested in checking equivalence of FSMs(finite state machines). Two FSMs are equivalent if and only if their responses are always equal with each other with respect to the same external stimuli. Equivalence checking FSMs makes complicated FSM be substituted for simpler one, if they are equivalent. We can also determine the system satisfies the requirements, if they are all written in FSMs. In this paper, we regard equivalence checking problem as model checking one. For doing so, we construct the product model $M ={M_A} {\beta}{M_B} from two FSMs ${M_A} and {M_B}$. And we also get the temporal logic formula ${\Phi}$ from the equivalence checking definition. Then, we can check with model checker whether if satisfies ${\Phi}$, written $M= {.\Phi}$. Two FSMs are equivalent, if $M= {.\Phi}$ Otherwise, it is not equivalent. In that case, model checker generates counterexamples which explain why FSMs are not equivalent. In summary, we solve the equivalence checking problem with model checking techniques. As a result of applying to several examples, we have many satisfiable results.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.41 no.4
• /
• pp.51-58
• /
• 2004

This paper proposes a new artificial immune approach to on-line hardware test which is the most indispensable technique for fault tolerant hardware. A novel algorithm of generating tolerance conditions is suggested based on the principle of the antibody diversity. Tolerance conditions in artificial immune system correspond to the antibody in biological immune system. In addition, antigen presenting cell (APC) is realized by Quine-McCluskey method in this algorithm and tolerance conditions are generated through GA (Genetic Algorithm). The suggested method is applied to the on-line monitoring of a typical FSM (a decade counter) and its effectiveness is demonstrated by the computer simulation.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.3
• /
• pp.201-207
• /
• 2008

This paper presents the implementation of a Tiling System about Preprocessing functions of JPEG 2000. The system covers the JPEG 2000 standard and is designed to determine the size of the image, to expand the image area and to split input image into several tiles. In order to split the input image with the progressive transmission into several tiles and transmit a tile of this image to others, this system store this image into Frame Memory. Therefore, this is designed as the Finite State Machine (FSM) to sequence through specific patterns of states in a predetermined sequential manner by using Verilog-HDL and be designed to handle a maximum 5M image. Moreover, for identifying image size for expansion, we propose several formula which are based on remainder after division (rem). we propose the true table which determines the size of the image input patterns by using results of these formula. Under the condition of TSMC 0.25um ASIC library, gate count is 18,725 and maximum data arrival time is 18.94 [ns].

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.2A
• /
• pp.137-146
• /
• 2005

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Interface modules for communication between system buses and IPs are required, since many IPs employ different protocols. Automatic generation of these interface modules would enhance designer's productivity and IP's reusability. This paper proposes an automatic interface generation system based on FSM generated from the protocol description of IPs. The proposed system provides the library modules for the standard buses to reduce the burdens of describing the protocols for data transfer from/to standard buses. Experimental results show that the area of the interface circuits generated by the proposed system had been increased slightly by 4.5% on the average when compared to manual designs. In the experiment, where bus clock is 100 Mhz and slave module clock is 34 Mhz, the latency of the interface had been increased by 7.1% in burst mode to transfer 16 data words. However, occupation of system bus can be reduce by 64.9%. A chip designer can generate an interface that improves the efficiency of system bus, by using this system.

• Proceedings of the KIEE Conference
• /
• 2011.07a
• /
• pp.1908-1909
• /
• 2011

Hand gesture recognition has been widely used in virtual reality and HCI (Human-Computer-Interaction) system, which is challenging and interesting subject in the vision based area. The existing approaches for vision-driven interactive user interfaces resort to technologies such as head tracking, face and facial expression recognition, eye tracking and gesture recognition. The purpose of this paper is to combine the finite state machine (FSM) and the gesture recognition method, in other to control Windows Media Player, such as: play/pause, next, pervious, and volume up/down.

• Proceedings of the Korean Operations and Management Science Society Conference
• /
• 2000.04a
• /
• pp.107-110
• /
• 2000

화학 박막 증착용(CVD : Chemical Vapor Deposition) 클러스터 장비는 다양한 공정 경로가 가능하며 물류 흐름이 매우 복잡해질 수 있다. 또한, 공정이 종료된 웨이퍼는 제한 시간 내에 챔버에서 꺼내져야만 한다. 클러스터 장비는 두 개의 팔을 가진 로봇이며, 빈 쪽 팔을 이용하여 공정이 종료된 웨이퍼를 꺼낸 후, 다른 쪽 팔을 이용하여 이전 공정에서 가져온 웨이퍼를 해당 공정에 넣어 주는 스왑(SWAP) 방식으로 운영된다. 이러한 스왑 방식에서는 로봇 작업 순서가 결정되어 진다. 그러나, 로봇의 팔 이외에 임시버퍼가 없고, 각 챔버는 엄격한 체제 시간 제약(Residency Time Constraint)을 가지고 있기 때문에 로봇의 작업 시점의 제어가 필요하다. 본 논문에서는 간단한 Earliest Starting 방식으로 로봇의 작업 시점을 제어한다고 가정했을 때, 스왑 방식을 운용하면서 체제 시간 제약을 만족하는 공정 시간들의 조건을 제시한다. 공정 시간은 엔지니어에 의해 다소 조정이 가능하므로 공정 시간들의 조건은 엔지니어에게 스케줄 가능한 공정 시간을 결정할 수 있도록 지원해 주는 시스템에 활용 가능하다. 또한, 본 논문에서는 FSM(Finite State Machine)을 이용하여 CTC(Cluster Tool Controller) 내부의 실시간 스케줄러 구현 방법을 제안한다.