• 제목/요약/키워드: Finger Gate

검색결과 33건 처리시간 0.016초

고전압 β-산화갈륨(β-Ga2O3) 전력 MOSFETs (High Voltage β-Ga2O3 Power Metal-Oxide-Semiconductor Field-Effect Transistors)

  • 문재경;조규준;장우진;이형석;배성범;김정진;성호근
    • 한국전기전자재료학회논문지
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    • 제32권3호
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    • pp.201-206
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    • 2019
  • This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

A $G_{4}$ Sequence within PHR1 Promoter Acts as a Gate for Cross-Talks between Damage-Signaling Pathway and Multi-Stress Response

  • Jang, Yeun-Kyu;Kim, Eun-Mi;Park, Sang-Dai
    • Animal cells and systems
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    • 제6권3호
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    • pp.271-275
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    • 2002
  • Rph1 and Gisl are damage-responsive repressors involved in PHR1 expression. They have two $C_{2}$H/ sub 2/ zinc finger motifs as putative DNA binding domains and N-terminal conserved domain with unknown function. They are also found in the human retinoblastoma binding protein 2 and the mouse jumonji- encoded protein. The repressors are able to bind to A $G_{4}$ sequence within a 39-bp sequence called upstream repressing sequence of PHR1 promoter (UR $S_{PHR1}$) responsible for the damage-response of PHR1. We report here that Rph1 is predominantly localized in the nucleus as examined by fluorescence microscopic analysis with GFP-Rph1 fusion protein. On the basis of the fact that the A $G_{4}$ sequence that is recognized by Rph1 and Gisl is also recognized by Msn2 and Msn4 in a process of stress response, we a1so tried to examine the in vivo function of A $G_{4}$ and the role of Msn2 and Msn4 in PHR1 expression. Our results demonstrate that Msn2 and Msn4 are actually required for the basal transcription of PHR1 expression but not for its damage induction. When A $G_{4}$ sequence was inserted into the minimal promoter of the cyc1-LacZ reporter, the increased LacZ expression was observed indicating its involvement in transcriptional activation. The data suggest that the A $G_{4}$ is primarily required for basal transcriptional activation of PHR1 or CYC1 promoter through the possible involvement of Msn2 and Msn4. However, since the A $G_{4}$ is also involved in the repression of PHR1 via Rphl and Gisl, it is proposed that A $G_{4}$ functions as either URS or upstream activating sequence (UAS) depending on the promoter context.t.

45nm CMOS 공정기술에 최적화된 저전압용 이득-부스팅 증폭기 기반의 1.1V 12b 100MS/s 0.43㎟ ADC (A 1.1V 12b 100MS/s 0.43㎟ ADC based on a low-voltage gain-boosting amplifier in a 45nm CMOS technology)

  • 안태지;박준상;노지현;이문교;나선필;이승훈
    • 전자공학회논문지
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    • 제50권7호
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    • pp.122-130
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    • 2013
  • 본 논문에서는 주로 고속 디지털 통신시스템 응용을 위해 고해상도, 저전력 및 소면적을 동시에 만족하는 45nm CMOS 공정으로 제작된 4단 파이프라인 구조의 12비트 100MS/s ADC를 제안한다. 입력단 SHA 회로에는 높은 입력 주파수를 가진 신호가 인가되어도 12비트 이상의 정확도로 샘플링할 수 있도록 게이트-부트스트래핑 회로가 사용된다. 입력단 SHA 및 MDAC 증폭기는 요구되는 DC 이득 및 높은 신호스윙을 얻기 위해 이득-부스팅 구조의 2단 증폭기를 사용하며, 넓은 대역폭과 안정적인 신호정착을 위해 캐스코드 및 Miller 주파수 보상기법을 선택적으로 적용하였다. 채널길이 변조현상 및 전원전압 변화에 의한 전류 부정합을 최소화하기 위하여 캐스코드 전류 반복기를 사용하며, 소자의 부정합을 최소화하기 위하여 전류 반복기와 증폭기의 단위 넓이를 통일하여 소자를 레이아웃 하였다. 또한, 제안하는 ADC에는 전원전압 및 온도 변화에 덜 민감한 저전력 기준 전류 및 전압 발생기를 온-칩으로 집적하는 동시에 외부에서도 인가할 수 있도록 하여 다양한 시스템에 응용이 가능하도록 하였다. 제안하는 시제품 ADC는 45nm CMOS 공정으로 제작되었으며 측정된 DNL 및 INL은 각각 최대 0.88LSB, 1.46LSB의 값을 가지며, 동적성능은 100MS/s의 동작속도에서 각각 최대 61.0dB의 SNDR과 74.9dB의 SFDR을 보여준다. 시제품 ADC의 면적은 $0.43mm^2$ 이며 전력소모는 1.1V 전원전압 및 100MS/s 동작속도에서 29.8mW이다.