• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.761-767
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• 1999

Poly-Si TFTs(polycrystalline silicon thin film transistors) fabricated on a low cost glass substrate have attracted a considerable amount of attention for pixel elements and peripheral driving circuits in AMLCS(active matrix liquid crystal display). In order to apply poly-Si TFTs for high resolution AMLCD, a high operating frequency and reliable circuit performances are desired. A new poly-Si TFT with CLBT(counter doped lateral body terminal) is proposed and fabricated to suppress kink effects and to improve the device stability. And this proposed device with BC(buried channel) is fabricated to increase ON-current and operating frequency. Although the troublesome LDD structure is not used in the proposed device, a low OFF-current is successfully obtained by removing the minority carrier through the CLBT. We have measured the dynamic properties of the poly-Si TFT device and its circuit. The reliability of the TFTs and their circuits after AC stress are also discussed in our paper. Our experimental results show that the BC enables the device to have high mobility and switching frequency (33MHz at $V_{DD}$ = 15 V). The minority carrier elimination of the CLBT suppresses kink effects and makes for superb dynamic reliability of the CMOS circuit. We have analyzed the mechanism in order to see why the ring oscillators do not operate by analyzing AC stressed device characteristics.

• Journal of Korea Foundry Society
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• v.40 no.3
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• pp.85-96
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• 2020

The effect of an aluminum scrap addition ratio on the tensile and solidification cracking properties of the AC4A aluminum alloy in the as-cast state and heat-treated state were investigated in this study. Generally, the expected problem of using scrap in aluminum casting is an increase of hydrogen and Fe element inside the aluminum melt. Another issue is an oxide film which has a weak interface with the molten aluminum and acts as potent nucleation sites for internal porosity and crack initiation. Solidification cracking is one of the critical defects that must be resolved to produce high quality castings. A conventional evaluation method for solidification cracking is a relative and qualitative analysis method which does not provide quantitative data on the thermal stress in the solidification process. Therefore, a newly designed solidification cracking test apparatus was used in this study, and the device can provide quantitative data. As a result, after conducting experiments with different scrap addition ratios (0%, 20%, 35%, 50%), the tensile strengths and elongations in the as-cast state were 214, 187.7, 182.1 and 170.4MPa and 4.6%, 3.4%, 3.1% and 2.3%, respectively. In the case of the T6 heat-treated state, the tensile strengths and elongations were 314.9, 294.6, 293.1 and 271.1MPa and 5.4%, 4.6%, 3.8% and 3.1%, respectively. The strength of the solidification cracking was 3.1, 2.4, 2.2and 1.6MPa as the scrap addition ratio increases.

• Journal of the Semiconductor & Display Technology
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• v.8 no.4
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• pp.65-69
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• 2009

Carbon nanotubes (CNTs) were coated with undoped zinc oxide (ZnO) or 5 wt% gallium-incorporated ZnO (GZO) using various deposition conditions. The CNTs were directly grown on conical-type tungsten substrates at $700^{\circ}C$ using inductively coupled plasma-chemical vapor deposition. The pulsed laser deposition technique was used to deposit the ZnO and GZO thin films with very low stress. Field-emission scanning electron microscopy and high-resolution transmission electron microscopy were used to monitor the variations in the morphology and microstructure of CNTs prior to and after ZnO or GZO coating. The formation of ZnO and GZO films on CNTs was confirmed using energy-dispersive x-ray spectroscopy. In comparison to the as-grown (uncoated) CNT emitter, the CNT emitter that was coated with a thin (10 nm) GZO film showed remarkably improved field emission characteristics, such as the emission current of $325\;{\mu}A$ at 1 kV and the threshold field of $1.96\;V/{\mu}m$ at $0.1\;{\mu}A$, and it also exhibited the highly stable operation of emission current up to 40 h.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.74-74
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• 2010

모바일 정보통신기기를 중심으로 전자패키지의 초소형화, 고집적화를 위해 플립칩 공법의 적용이 증가되고 있는 추세이다. 플립칩 패키징 접합소재로는 솔더, ICA(Isotropic Conductive Adhesive), ACA(Anisotropic Conductive Adhesive), NCA(Non Conductive Adhesive) 등과 같은 다양한 접합소재가 사용되고 있다. 최근에는 언더필을 사용하는 플립칩 공법보다 미세피치 대응성을 위해 NCP를 이용한 플립칩 공법에 대한 요구가 증가되고 있는데, NCP의 상용화를 위해서는 공정성과 함께 신뢰성 확보가 필요하다. 본 연구에서는 LDI(LCD drive IC) 모듈을 위한 COF(Chip-on-Film) 플립칩 패키징용 NCP 포뮬레이션을 개발하고 이를 적용한 COF 패키지의 신뢰성을 조사하였다. 테스트베드는 면적 $1.2{\times}0.9mm$, 두께 $470{\mu}m$, 접속피치 $25{\mu}m$의 Au범프가 형성된 플리칩 실리콘다이와 접속패드가 Sn으로 finish된 폴리이미드 재질의 flexible 기판을 사용하였다. NCP는 에폭시 레진과 산무수물계 경화제, 이미다졸계 촉매제를 사용하여 다양하게 포뮬레이션을 하였다. DSC(Differential Scanning Calorimeter), TGA(Thermogravimetric Analysis), DEA(Dielectric Analysis) 등의 열분석장비를 이용하여 NCP의 물성과 경화거동을 확인하였으며, 본딩 후에는 보이드를 평가하고 Peel 강도를 측정하였다. 최적의 공정으로 제작된 COF 패키지에 대한 HTS (High Temperature Stress), TC (Thermal Cycling), PCT (Pressure Cooker Test)등의 신뢰성 시험을 수행한 결과 양산 적용 가능 수준의 신뢰성을 갖는 것을 확인할 수 있었다.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.20 no.2
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• pp.137-142
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• 1984

An experimental study has been performed on the heat transfer characteristics of condensation by the injecting steam flow in the tube. The comparison between results of experimental data and available data concerning equivalent Reynolds number has studied. As the result, the followings were obtained. 1. The shear stress of the radial direction in the tube when the injecting steam flow was condensed can be written as root($\tau$sub(0)/$\tau$sub(0v))=1+1.46X sub(tt) super(0.20). 2. The effect of the heat transfer in the injecting steam flow was less than the value of equivalent Reynolds number. The reason are the nonuniform fluid film of the axial and radial direction in the tube. 3. The value of N sub(u) by the heat transfer of condensation can be written as N sub(u)=1.08$\times$[{$\rho$ sub(l) d/$\mu$ sub(l)}/{$\delta$+(2.5/P sub(rl)) ln(y sub(i)/$\delta$)}]$\times${$\tau$ sub(0)/ $\rho$ sub(l)} super(1/2).

• Journal of the Microelectronics and Packaging Society
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• v.13 no.2 s.39
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• pp.9-13
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• 2006

The copper lines in COF are usually fabricated by subtractive method. As the width of lines are smaller, the subtractive method has a lateral etching problems. In semi-additive method, copper lines are fabricated by lithographic technique followed by electroplating method. Fine line patterns of $10-40{\mu}m$ were used for this study. Two different types of thick photoresist, AZ4620 and PMER900, were employed for PR mold. Copper lines were fabricated by electroplating method. The crack were found in fine copper lines due to high residual stress when normal copper electroplating bath were used. The via filling copper electroplating bath were replaced the normal electroplating bath and then cracks were not found in the fine copper lines. During substrate etching, the lateral etching of copper lines were not occurred.

• Korean Journal of Materials Research
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• v.12 no.12
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• pp.918-923
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• 2002

In this work, CdTe films were deposited on CdS/ITO/glass substrate by a close spaced sublimation (CSS) method. A $Cu_2$Te layer was deposited on the CdTe film by evaporating $Cu_2$Te powder. Then the samples were annealed for p+ ohmic contact. TEM and XRD analysis showed that $CdTe/Cu_2$Te interface exhibited different forms with various annealing temperature. A good p+ ohmic contact was achieved when the annealing temperature was between $180^{\circ}C$ to $200^{\circ}C$. Best cell efficiency of 12.34% was obtained when post annealing temperature was $200^{\circ}C$ for 5 min. Thermal stress test of the CdS/CdTe cells with carbon back contact showed that the $Cu_2$Te contact was stable at $50^{\circ}C$ in $N_2$ and was slowly degraded at $100^{\circ}C$ in $N_2$. In comparison to the conventional carbon contact, the $Cu_2$Te contact showed a better thermal stability.

• Progress in Superconductivity
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• v.8 no.2
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• pp.181-185
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• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.

• Journal of the Korean Vacuum Society
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• v.9 no.4
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• pp.389-393
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• 2000

Effects of Co addition and heat treatment on the magnetic properties of Fe-Si-B thin films were investigated. The compositions of metalloids, i.e, B and Si, in the alloys were kept 10 at.% each. Heat treatments were carried out in the temperature range from 100 to $300^{\circ}C$ for up to 60 min. Amorphous thin films of FeCoSiB were deposited on the water-cooled substrates by dc magnetron sputtering. The composition of thin films was controlled by placing proper number of pellets of alloying elements and analyzed by ICP, resulting in $Fe_{80-X}Co_ XB_{10}Si_{10}$ (X=8~18 at.%). Saturation magnetization of the alloys increased as Co concentration increased up to 10 at.% and then decreased with further increase of Co concentration. However, coercive force of the films decreased with the increase of Co concentration. Furthermore, the coercive force was also reduced by the annealing due to the residual stress relief.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.110-110
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• 2010

현재 박막 트랜지스터는 비정질 실리콘 기반의 개발이 주를 이루고 있으며, 이 비정질 실리콘은 성막공정이 간단하고 대면적에 용이하지만 전기적인 특성이 우수하지 않기 때문에 디스플레이의 적용에 어려움을 겪고 있다. 이에 따라 poly-Si을 이용한 박막 트랜지스터의 연구가 진행되고 있는데, 이는 공정온도가 높고, 대면적에의 응용이 어렵다. 따라서 앞으로 저온 공정이 가능하며 대면적 응용이 용이한 박막 트랜지스터의 연구가 필수적이다. 한편 최근 박막 트랜지스터의 채널층으로 사용되는 물질에는 oxide 기반의 ZnO, SnO2, In2O3 등이 주로 사용되고 있고, 보다 적합한 채널층을 찾기 위한 연구가 많이 진행되어 왔다. 최근 Hosono 연구팀에서 IGZO를 채널층으로 사용하여 high mobility, 우수한 on/off ratio의 특성을 가진 소자 제작에 성공함으로써 이를 시작으로 IGZO의 연구 또한 세계적으로 활발한 연구가 이루어지고 있다. 특히, ZnO는 wide band gap (3.37eV)을 가지고 있어 적외선 및 가시광선의 투과율이 좋고, 전기 전도성과 플라즈마에 대한 내구성이 우수하며, 낮은 온도에서도 성막이 가능하다는 특징을 가지고 있다. 그러나 intrinsic ZnO 박막은 bias stress 같은 외부 환경이 변했을 경우 전기적인 성질의 변화를 가져올 뿐만 아니라 고온에서의 공정이 불안정하다는 요인을 가지고 있다. ZnO의 전기적인 특성을 개선하기 위해 본 연구에서는 hafnium을 doping한 ZnO을 channel layer로 소자를 제작하고 전기적 특성을 평가하였다. 이를 위해 DC magnetron sputtering을 이용하여 ZnO 기반의 박막 트랜지스터를 제작하였다. Staggered bottom gate 구조로 ITO 물질을 전극으로 사용하였으며, 제작된 소자는 semiconductor analyzer를 이용하여 출력특성과 전이 특성을 평가하였으며, ZnO channel layer 증착시 hafnium이 도핑 되는 양을 조절하여 소자를 제작한 후 intrinsic ZnO의 소자 특성과 비교 분석하였다. 그 결과 hafnium을 doping 시킨 소자의 field effect mobility가 $6.42cm^2/Vs$에서 $3.59cm^2/Vs$로 낮아졌지만, subthreshold swing 측면에서는 1.464V/decade에서 0.581V/decade로 intrinsic ZnO 보다 좋은 특성을 나타냄을 알 수 있었다. 그리고 intrinsic ZnO의 경우 외부환경에 대한 안정성 문제가 대두되고 있는데, hafnium을 도핑한 ZnO의 경우 temperature, bias temperature stability, 경시변화 등의 다양한 조건에서의 안정성이 확보된다면 intrinsic ZnO 박막트랜지스터의 문제점을 해결할 수 있는 물질로 될 것이라고 기대된다.