• 한국통신학회논문지
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• 제33권12A호
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• pp.1172-1176
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• 2008

본 논문에서는 상용 DSP를 기반으로 하여 SDR용 스마트 안테나 시스템의 듀얼 모드 채널 카드를 구현하였다. SDR(Software Define Radio) 기술은 공통된 하드웨어 플랫폼에 소프트웨어를 다운로드하여 사용자가 원하는 모드로 재구성이 가능하게 하는 기술이다. 채널 카드는 고속 데이터 전송을 위한 차세대 이동통신 방식인 WiBro(Wireless Broadband)와 HSDPA(High Speed Downlink Packet Access) 통신 모드를 지원하며, 스마트 안테나 기술이 적용된 듀얼 모드 기지국 시스템의 핵심인 모뎀 카드로 사용된다. 본 논문에서는 WiBro 시스템과 HSDPA 시스템으로 구현된 채널 카드의 구조를 설명하고, 구현된 채널 카드의 성능 검증을 위해 상용 통신 규격인 WiBro와 HSDPA시스템에서의 성능을 알아본다.

• Journal of Communications and Networks
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• 제13권5호
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• Journal of Biosystems Engineering
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• 제33권5호
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• pp.317-325
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• 2008

The electrocardiogram (ECG) measurement system consists of I/O interface to input the ECG signals from two electrodes, FPGA (Field programmable gate arrays) module to process the signal conditioning, and real time module to control the system. The algorithms based on wavelet transform were developed to remove the noise of the ECG signals and to determine the QRS-waves. Triangular wave tests were conducted to determine the optimal factors of the wavelet filter by analyzing the SNRs (signal to noise ratios) and RMSEs (root mean square errors). The hybrid rule, soft method, and symlets of order 5 were selected as thresholding rule, thresholding method, and mother wavelet, respectively. The developed wavelet filter showed good performance to remove the noise of the triangular waves with 10.98 dB of SNR and 0.140 mV of RMSE. The ECG signals from a total of 6 subjects were measured at different measuring postures such as lying, sitting, and standing. The durations of QRS-waves, the amplitudes of R-waves, the intervals of RR-waves were analyzed by using the finite impulse response (FIR) filter and the developed wavelet filter. The wavelet filter showed good performance to determine the features of QRS-waves, but the FIR filter had some problems to detect the peaks of Q and S waves. The measuring postures affected accuracy and precision of the ECG signals. The noises of the ECG signals were increased due to the movement of the subject during measurement. The results showed that the wavelet filter was a useful tool to remove the noise of the ECG signals and to determine the features of the QRS-waves.

• 한국통신학회논문지
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• 제33권4A호
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• pp.387-393
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• 2008

본 논문에서는 TDD HSDPA(Time Division Duplex High Speed Downlink Packet Access)와 WiBro(Wireless Broadband Portable Internet) 와 같은 이동통신 규격을 지원하는 SDR(Software Defined Radio) 단말 모뎀 플랫폼을 제안한다. 제안하는 SDR 플랫폼은 DSP, FPGA, 마이크로프로세서 등 프로그래밍 가능한 소자들을 채용하여 HSDPA와 WiBro와 같은 기능을 담당하는 프로그램 등이 하드웨어 플랫폼 상에 다운로드 가능하도록 하였다. 제안하는 플랫폼은 이동통신네트워크의 멀티모드 단말시스템을 위한 물리계층 규격의 기능검증 등에 사용될 수 있다. 본 논문은 먼저 HSDPA와 WiBro 시스템의 물리계층 수신구조를 설명하고, 제안하는 SDR 플랫폼의 하드웨어 구현 방법과 각 모드에 요구되는 기능과 구현한 하드웨어 플랫폼 상에서의 최적화된 신호 흐름의 설계방법을 제시한다. 마지막으로 테스트신호를 이용한 루프백(loopback) 테스트를 통하여 제안한 SDR 플랫폼 상에 동작하는 각 모드 별 링크 성능을 보여준다. 제시된 실험 성능은 컴퓨터 시뮬레이션 성능과 비교하였다.

• 한국전자파학회논문지
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• 제29권2호
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• pp.138-141
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• 2018

본 논문에서는 FPGA를 이용하여 디지틀 방식으로 영상 레이다에 사용하는 주파수 변조된 첩(Chirp) 신호를 생성하고, 이 신호를 I-Q 변조하여 RF 신호로 변환 한 후 24 주파수 체배기로 체배하여 94 GHz W-대역에서 광대역 첩 신호발생 장치의 설계, 제작한 연구 결과를 제시한다. 개발된 첩 발생기는 94 GHz의 캐리어 주파수와 960 MHz의 대역폭을 가지는 주파수 변조된 신호이며, 평탄도는 IF단(3.9 GHz)에서 1 dB 이내, W-대역에서 2 dB 이내 그리고 3 W의 출력을 보여주고 있다.

• 한국정보과학회논문지:시스템및이론
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• 제31권8호
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Nuclear Engineering and Technology
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• 제56권2호
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• pp.745-752
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• 2024

A method for gamma/neutron event classification based on frequency-domain analysis for mixed radiation environments is proposed. In contrast to the traditional charge comparison method for pulse-shape discrimination, which requires baseline removal and pulse alignment, our method does not need any preprocessing of the digitized data, apart from removing saturated traces in sporadic pile-up scenarios. It also features the identification of neutron events in the detector's full energy range with a single device, from thermal neutrons to fast neutrons, including low-energy pulses, and still provides a superior figure-of-merit for classification. The proposed frequency-domain analysis consists of computing the fast Fourier transform of a triggered trace and integrating it through a simplified version of the transform magnitude components that distinguish the neutron features from those of the gamma photons. Owing to this simplification, the proposed method may be easily ported to a real-time embedded deployment based on Field-Programmable Gate Arrays or Digital Signal Processors. We target an off-the-shelf detector based on a small CLYC (Cs2LiYCl6:Ce) crystal coupled to a silicon photomultiplier with an integrated bias and preamplifier, aiming at lightweight embedded mixed radiation monitors and dosimeter applications.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1022-1027
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• 2003

The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.