• 전기학회논문지
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• 제56권4호
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• pp.799-808
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• 2007

BACnet is an international standard communication protocol especially designed for building automation and control systems. BACnet uses the Master-Slave/Token-Passing (MS/TP) protocol as one of its field-level networks. A BACnet MS/TP field controller prototype and MS/TP network monitoring system are developed in this study. This report introduces the design and implementation methodology of a BACnet MS/TP field controller hardware, firmware and protocol stack. This report also presents the implementation methodology of BACnet MS/TP network monitoring system using VTS (Visual Test Shell). The methodologies introduced in this report will facilitate the develop and implementation of the BACnet-based control systems in building automation area.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 추계학술대회 논문집
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• pp.2090-2095
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• 2008

Ubiquitous information technology creates new space connected to electronic and physical space and makes new life pattern come true. Although it is expected that ubiquitous technology will lead significant changes on various life fields, relevant studies on its market needs, customer needs in social and cultural context and its necessity at organizational level have been passively carried out. What is worse, IT technology application scheme in railway field has not fully established since railway field's technology development is mainly focused on hardware compared with road and air traffic. In order to apply ubiquitous technology to railway field, therefore, it is required to identify ubiquitous technology functions which applicable to railway field and to establish ubiquitous rail system implementation scheme for end users. In this paper, we suggested implementation scheme for u-Rail which sorts railway industry by its components in order to implement service centered ubiquitous technology to each railway industry field.

• Steel and Composite Structures
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• 제7권4호
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• pp.263-278
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• 2007

A finite element implementation of the modified compression field theory (MCFT) using a tangential formulation is presented in this work. Previous work reported on implementations of MCFT has concentrated mainly on secant formulations. This work describes details of the implementation of a modular algorithmic structure of a reinforced concrete constitutive model in nonlinear finite element schemes that use a Jacobian matrix in the solution of the nonlinear system of algebraic equations. The implementation was verified and validated using experimental and analytical data reported in the literature. The developed algorithm, which converges accurately and quickly, can be easily implemented in any finite element code.

• 정보보호학회논문지
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• 제9권4호
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• pp.3-10
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• 1999

유한체(Galois fields)가 타원곡선 암호법 coding 이론 등에 응용되면서 유한체의 연 산은 더많은 관심의 대상이 되고 있다. 유한체의 연산은 표현방법에 많은 영향을 받는다. 즉 최적 정규기 저는 하드웨 어 구현에 용이하고 Trinomial을 이용한 다항식 기저는 소프트웨어 구현에 효과적이다. 이논문에서는 새로운 변형된 다항식 기저를 소개하고 AOP를 이용한 경우 하드웨어 구현에 효과적인 최 적 정규기저와 의 변환이 위치 변화로 이루어지고 또한 이것을 바탕으로 한 유한체의 연산이 소프트웨어적 으로 효율적 임을 보인다. More concerns are concentrated in finite fields arithmetic as finite fields being applied for Elliptic curve cryptosystem coding theory and etc. Finite fields arithmetic is affected in represen -tation of those. Optimal normal basis is effective in hardware implementation and polynomial field which is effective in the basis conversion with optimal normal basis and show that the arithmetic of finite field with the basis is effective in software implementation.

• 디지털산업정보학회논문지
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• 제16권2호
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• 대한전자공학회논문지SD
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• 제42권1호
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• pp.57-67
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• 2005

고속 스칼라곱 연산은 타원곡선 암호 응용을 위해서 매우 중요하다. 보안 상황에 따라 유한체의 크기를 변경하려면 타원곡선 암호 보조프로세서가 크기 가변 유한체 연산 장치를 제공하여야 한다. 크기 가변 유한체 연산기의 효율적인 연산 구조를 연구하기 위하여 전형적인 두 종류의 스칼라곱 연산 알고리즘을 FPGA로 구현하였다. Affine 좌표계 알고리즘은 나눗셈 연산기를 필요로 하며, projective 좌표계 알고리즘은 곱셈 연산기만 사용하나 중간 결과 저장을 위한 메모리가 더 많이 소요된다. 크기 가변 나눗셈 연산기는 각 비트마다 궤환 신호선을 추가하여야 하는 문제점이 있다. 본 논문에서는 이로 인한 클록 속도저하를 방지하는 간단한 방법을 제안하였다. Projective 좌표계 구현에서는 곱셈 연산으로 널리 사용되는 디지트 serial 곱셈구조를 사용하였다. 디지트 serial 곱셈기의 크기 가변 구현은 나눗셈의 경우보다 간단하다. 최대 256 비트 크기의 연산이 가능한 크기 가변 유한체 연산기를 이용한 암호 프로세서로 실험한 결과, affine 좌표계 알고리즘으로 스칼라곱 연산을 수행한 시간이 6.0 msec, projective 좌표계 알고리즘의 경우는 1.15 msec로 나타났다. 제안한 타원곡선 암호 프로세서를 구현함으로써, 하드웨어 구현의 경우에도 나눗셈 연산을 사용하지 않는 projective 좌표계 알고리즘이 속도 면에서 우수함을 보였다. 또한, 메모리의 논리회로에 대한 상대적인 면적 효율성이 두 알고리즘의 하드웨어 구현 면적 요구에 큰 영향을 미친다.

• ETRI Journal
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• 제42권4호
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• pp.534-548
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• 2020

This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

• 통상정보연구
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• 제8권2호
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• pp.119-139
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• 2006

The purpose of this research is to analyze four models of global e-trade implementation which was suggested at the advance research of implementation global e-Trade with major trading countries. The main outcomes of this empirical study are as follows. For realizing global e-trade of G-Networking model country we have to implement e-trade in the field of "import & logistics". And for realizing global e-trade of P-Networking model country, it need to try in "settlement & clearance". Furthermore, for realizing global e-Trade of G-Penetration model country, we have known that the field of "import & logistics" would be implemented. Finally for realizing global e-Trade of P-Penetration model country, "settlement & clearance" could be implemented. Also, this study suggests that we have to do negotiation with China and Japan at first, and to try the area of settlement & clearance to implement the global e-Trade with Korea's 10 major trading countries.

• 디지털산업정보학회논문지
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• 제18권1호
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• 한국전자통신학회논문지
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• 제12권6호
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• pp.1181-1188
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• 2017

수체의 단수와 기본단수계는 RSA 암호계에서는 400자리 이상의 큰 수가 소수인지를 판별하는 소수판정법과 그 수를 소인수분해하는 데에 사용되는 다양한 수체선별법에 사용되며, 복소이차체를 기반으로 하는 암호계에서는 이데알의 곱셈과정과 류수(class number)를 계산하는 과정 등 다양한 암호계에서 사용되고 있다. 본 논문에서는 기본단수계를 이용하는 암호계의 구현시간과 공간을 줄이기 위하여, 수체의 기본단수계의 존재성을 증명한 Dirichlet의 정리와 몇 가지 기본단수계의 성질을 중심으로 우리가 제안하는 기본단수계의 생성 과정을 소개한다. 그리고 그에 따른 기본단수계의 H/W 구현의 시간과 공간을 최소화할 수 있는 효율적인 기본단수계의 생성알고리즘과 그 알고리즘을 H/W 상에서 구현한 결과를 제시한다.