• Title/Summary/Keyword: Fault correction

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A Simple Fault Correction Method for Rotor Position Detection of Brushless DC Motor using a Latch Type Hall Effect Sensor

  • Baik In-Cheol;Joo Hyeong-Gil
    • Journal of Power Electronics
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    • v.5 no.1
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    • pp.62-66
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    • 2005
  • A simple fault correction method for rotor position detection of a brushless DC(BLDC) motor with trapezoidal back EMF(electromotive force) using a Hall effect latch unit is presented. The reason why the Hall effect latch unit does not operate properly during the startup of a BLDC motor is thoroughly explained. To solve this problem, a simple code change method and its hardware implementation issues are proposed and discussed.

RBR Based Network Configuration Fault Management Algorithms using Agent Collaboration (에이전트들 간의 협력을 통한 RBR 기반의 네트워크 구성 장애 관리 알고리즘)

  • Jo, Gwang-Jong;An, Seong-Jin;Jeong, Jin-Uk
    • The KIPS Transactions:PartC
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    • v.9C no.4
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    • pp.497-504
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    • 2002
  • This paper proposes fault diagnosis and correction algorithms using agent collaboration, and a management model for managing network configuration faults. This management model is composed of three processes-fault detection, fault diagnosis and fault correction. Each process, based on RBR, operates on using rules which are consisted in Rule-based Knowledge Database. Proposed algorithm selves the complex fault problem that a system could not work out by itself, using agent collaboration. And the algorithm does efficiently diagnose and correct network configuration faults in abnormal network states.

Implementation of High Reliable Fault-Tolerant Digital Filter Using Self-Checking Pulse-Train Residue Arithmetic Circuits (자기검사 Pulse별 잉여수연산회로를 이용한 고신뢰화 Fault Tolerant 디지털필터의 구성에 관한 연구)

  • 김문수;손동인;전구제
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.2
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    • pp.204-210
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    • 1988
  • The residue number system offers the possibility of high-speed operation and error detection/correction because of the separability of arithmetic operations on each digit. A compact residue arithmetic module named the self-checking pulse-train residue arithmetic circuit is effectively employed as the basic module, and an efficient error detection/correction algorithm in which error detection is performed in each basic module and error correction is performed based on the parallelism of residue arithmetic is also employed. In this case, the error correcting circuit is imposed in series to non-redundant system. This design method has an advantage of compact hardware. Following the proposed method, a 2nd-order recursive fault-tolerant digital filter is practically implemented, and its fault-tolerant ability is proved by noise injection testing.

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Fault Current Calculation and Coordination by IEC Standards (IEC 표준에 의한 고장전류 계산과 보호협조)

  • Son, Seok-Geum
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.28 no.12
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    • pp.6-12
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    • 2014
  • The safety and reliability of the power system short-circuit current, the short-circuit current depends on the failure to obtain the objective is to quickly eliminate the breaking capacity of the circuit-breaker selection of the cable, the insulation of electrical equipment and protective relay an important factor in determining the level correction and protective relay selection scheme to be meaningful. Standards used in the domestic circuit breaker is applied to the production of IEC standard, but the American National Standards (ANSI / IEEE) by NEMA specification of the fault current calculations and the application of the asymmetric coefficient Korea. Therefore, in this paper, the IEC 60909 standard IEC breaker fault current calculation method and the method for selection of system configurations reviewed and protection system for reviewing the configuration of various protective relays appropriate correction and the correction value is main protection, back-up protection the equipment so that the period of protection relay coordination to minimize accidents and accident protection to minimize interruptions proposed for cooperation.

An Experimental Study on Operation Setting Optimization of Circuit Breaker for Improving Safety on DC Railroad Feeder System (직류철도 급전계통의 안전성 향상을 위한 차단기 동작 최적 설정의 실험적 고찰)

  • Lee, Jae-Bong;Jung, No-Geon;Kim, Jae-Moon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.3
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    • pp.526-531
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    • 2016
  • This paper presents an experimental study on the optimal settings for the selected DC fault relay (50F) to improve the operating performance for the high-speed circuit breaker on DC feeding system which ensure safety within rolling stock maintenance depot. In this study, current supplied to overhead contact wire was calculated on 1 ms interval to analyze the correction values of DC fault selective relay for the operation of current supply cutout. Particularly, standards for the accurate detection of accidents between an electric railway vehicle and the electric power facilities are shown by investigating the optimal correction values for detection of fault current, and the results indicated that it takes about 213 ms for the DC fault selective relay(50F) to fully open. In the future, the correction values of DC fault selective relay suggested in this paper will be used as the reference values of protective relay for the safe operation of DC electric railroad system such as urban railway.

A Series Arc Fault Detection Strategy for Single-Phase Boost PFC Rectifiers

  • Cho, Younghoon;Lim, Jongung;Seo, Hyunuk;Bang, Sun-Bae;Choe, Gyu-Ha
    • Journal of Power Electronics
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    • v.15 no.6
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    • pp.1664-1672
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    • 2015
  • This paper proposes a series arc fault detection algorithm which incorporates peak voltage and harmonic current detectors for single-phase boost power factor correction (PFC) rectifiers. The series arc fault model is also proposed to analyze the phenomenon of the arc fault and detection algorithm. For arc detection, the virtual dq transformation is utilized to detect the peak input voltage. In addition, multiple combinations of low- and high-pass filters are applied to extract the specific harmonic components which show the characteristics of the series arc fault conditions. The proposed model and the arc detection method are experimentally verified through a boost PFC rectifier prototype operating under the grid-tied condition with an artificial arc generator manufactured under the guidelines for the Underwriters Laboratories (UL) 1699 standard.

A Study on Correction of the Protective Relay Equipped in the Dedicated Line Used for Connecting Distributed Generators to Power Network (분산전원 계통 연계 전용선로에 설치된 보호 계전기의 정정에 관한 연구)

  • Jeong, Jong-Chan;Jang, Sung-Il;Choi, Don-Man;Kim, Kwang-Ho
    • Proceedings of the KIEE Conference
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    • 2002.11b
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    • pp.141-144
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    • 2002
  • This paper describes the correction of the protective relay equipped in the dedicated line used for connecting distributed generators (DG) to power grid. The fault current measured in a relaying point might be changed according to the fault conditions. Generally, the fault current of the line to line fault or the line to ground fault at the dedicated line is much higher than the protective set value due to the large fault level. However. when the high impedance fault is occurred in the dedicated line, we may not detect it because its fault level can be lower than the generating capacity of DG. And, the protective relay with conventional set value may generate a trip signal for insertion of DG due to the large transient characteristics of generators. Through the various simulations such as the fault in the dedicated line and the insertion of DG, we show that it would be necessary to modify the protective relay set value for detecting the high impedance fault occurred in the dedicated line and for preventing the mis-operation of protective relay caused by the insertion of DG.

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A Study on the Improved Protective Relaying Algorithm Applied in the Linked System Interconnecting Wind Farm with the Utilities (풍력발전단지 연계 전용선로 보호계전방식의 향상에 대한 연구)

  • 장성일;김광호;권혁완;김대영;권혁진
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.52 no.12
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    • pp.675-683
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    • 2003
  • This paper describes the correction strategy of an overcurrent relay applied in the linked line for interconnecting wind farm with utility power networks in order to improve the capability of a fault detection. The fault current measured in a relaying point might vary according to the fault conditions. Generally, the current of the line to line fault or the line to ground fault in the linked line is much higher than the set value of protective relay due to the large fault level. However, when the high impedance fault occurs in the linked line, we can't detect it by conventional set value because its fault level may be lower than the generating capacity of wind farm. And, the protective relay with conventional set value may generate a trip signal for the insertion of wind turbine generators due to the large transient characteristics. In order to solve above problems and improve protective relaying algorithms applied in the linked line, we propose a new correction strategy of the protective relay in the linked line. The presented method can detect the high impedance fault which can't be detected by conventional relay set value and may prevent the mis-operation of protective relay caused by the insertion of wind farm.

Fault Tolerant Cryptography Circuit for Data Transmission Errors (데이터 전송 오류에 대한 고장 극복 암호회로)

  • You, Young-Gap;Park, Rae-Hyeon;Ahn, Young-Il;Kim, Han-Byeo-Ri
    • The Journal of the Korea Contents Association
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    • v.8 no.10
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    • pp.37-44
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    • 2008
  • This paper presented a solution to encryption and decryption problem suffering data transmission error for encrypted message transmission. Block cypher algorithms experience avalanche effect that a single bit error in an encrypted message brings substantial error bits after decryption. The proposed fault tolerant scheme addresses this error avalanche effect exploiting a multi-dimensional data array shuffling process and an error correction code. The shuffling process is to simplify the error correction. The shuffling disperses error bits to many data arrays so that each n-bit data block may comprises only one error bit. Thereby, the error correction scheme can easily restore the one bit error in an n-bit data block. This scheme can be extended on larger data blocks.

An Quality Management Effort Estimation Model Based on Defect Filtering Concept (결점 필터링 개념 기반 품질관리 노력 추정 모델)

  • Lee, Sang-Un
    • Journal of the Korea Society of Computer and Information
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    • v.17 no.6
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    • pp.101-109
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    • 2012
  • To develop high quality software, quality control plan is required about fault correction that is latent within software. We should describe fault correction profile properly for this. The tank and pipe model performs complex processes to calculate fault that is remove and escapes. Also, we have to know in which phase the faults were inserted, removed and escaped and know the fault detection rate at any phases. To simplify such complex process, this paper presented model to fault filtering concept. Presented model has advantage that can describe fault more shortly because need not to consider whether was involved in fault that escaped fault is inserted at any step at free step. Also, presented effort estimating model that do fetters in function of fault removal quality and productivity measure and is required in fault detection.