• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.166-168
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• 2005

This paper presents a new numerical algorithm devoted to one window onto fault location calculation in time domain. It is based on two terminal data processing and it is derived on the synchronized phasor measured from the GPS connected the trans-mission line. The data is obtained by the testing through EMTP (Electromagnetic Tran- sient Program). The proposed the algorithm is estimated using linear least error squares method. The results of the algorithm testing through computer simulation (MATLAB) are presented.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1783-1785
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• 2001

With the 4-MJ synthetic testing facilities completed, KERI can perform the circuit breaker testing up to 420 kV, 50 kA ratings. The short-line fault test is one of the necessary test items which are required for the circuit breaker, and in order to perform the short-line fault test KERI(Korea Electrotechnology Institute) has used the "new artificial line" which has small dimension and is easy to generate the saw-tooth wave. This paper describes the following items of the new artificial line. -Description of 4-kinds of artificial lines and determination of the circuit parameter of artificial line. -TRV characteristics of saw-tooth waves for each circuit. -KERI's artificial line.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1710-1715
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• 2014

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.1948-1957
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• 1996

The conformance testing of communication protocol is the process to evaluate whether the protocol implemented is identified with standard specification. By evaluating how generated test cases detect many faults, it can be used with standard estimating efficiency of conformance testing. The method that evaluates the capability of fault coverage for test cases, has been researched by mathematical analysis and simulation. In this paper, we pointed out the problem of existing method and proposed new evaluation model of fault covergage for test case which generated by foult model. Also, we analyzed the results comparing to the existing evaluation method and proved its validity.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.11
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• pp.1545-1550
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• 2014

Fault detection and diagnosis (FDD) of photovoltaic (PV) power systems is one of significant techniques for reducing economic loss due to abnormality occurred in PV modules. This paper presents a new FDD method against PV power systems by using statistical comparison. This comparative approach includes deviation signals between the outputs of two neighboring PV modules. We first define a binary hypothesis testing under such deviation and make use of a generalized likelihood ratio testing (GLRT) theory to derive its FDD algorithm. Additionally, a recursive computational mechanism for our proposed FDD algorithm is presented for improving a computational effectiveness in practice. We carry out a real-time experiment to test reliability of the proposed FDD algorithm by utilizing a lab based PV test-bed system.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.14-21
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• 1997

In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the delay-optimized design in order to have the same defect-level for delay faults as the non-optimized design, while the system clock time is the same for both designs.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.343-346
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• 2000

When a feedback bridging fault is activated, oscillation may be generated in output signal lines. If the oscillation is generated, the fault may not be detected by logic testing. Thus, in the past we proposed a current sensor to detect feedback bridging faults by supply current testing. The sensor circuit design requires the maximum frequency of oscillation which is generated when feedback bridging fault is excited as a specification. In this paper, an estimation method of the oscillation frequency is proposed. Also, it is shown by some experiments that the frequency obtained by the method can be used for the sensor design.

• Journal of information and communication convergence engineering
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• v.3 no.1
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• pp.28-32
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• 2005

In this paper, we propose a novel test method to effectively detect hard and soft faults in CMOS 2-stage op-amps. The proposed method uses a very high frequency sinusoidal signal that exceeds unit gain bandwidth to maximize the fault effects. Since the proposed test method doesn't require any complex algorithms to generate the test pattern and uses only a single test pattern to detect all target faults, therefore test costs can be much reduced. The area overhead is also very small because the CUT is converted to a unit gain amplifier. Using HSPICE simulation, the results indicated a high degree of fault coverage for hard and soft faults in CMOS 2-stage op-amps. To verify this proposed method, we fabricated a CMOS op-amp that contained various short and open faults through the Hyundai 0.65-um 2-poly 2-metal CMOS process. Experimental results for the fabricated chip have shown that the proposed test method can effectively detect hard and soft faults in CMOS op-amps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2383-2390
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• 1998

As network provides diverse functionalities recently, many rpotocol standards have become complex and many implementations have appeared. Such trends require us to test th econformance of implementations, called the conformance testing. Many researches have been performed on generating test sequence and on fualt masking base don T,U,D,W methods. At this jpoint, te new problem is suggeste dwhich is calle dthe completenes s criteria. The test sequences for the conformance testing have come up with this problem as well as fault masking. In this paper, we suggest the method of generating the preverified test sequence which can avoid the completeness criteria problem. The preverified test sequence is much more reliable than others by using the preverified edge. For the reliability of conformance testing, we define the immunity of the test sequence and provide the clue for the analysis of the test results using the immunity. The analysis of the results makes it possible for us to test the implementation again with more reliability. Also, the preverified test sequence is flexible so that it is combined with the fault-tolerant sequence for fault masking.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.319-321
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• 2001

When the fault occurred at distribution system, the restoration was late. There are 2 reasons The one is the error of fault location the other is multiple possible candidates of fault location. This paper presents two of new techniques for diagnosing fault regions. The proposed diagnosis scheme is capable of accurately identifying the location of fault upon its occurrence. based on the integration of information available from protective devices and measured load current change at the substation. In this paper expert system for real fault region is presented using these facts. Testing of the developed system using EMTP Simulation Model has demonstrated.