• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1169-1172
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• 1998

We designed an ALU(Airthmetic Logic Unit) with BIST(Built-In Self Test), which is suitable for 32-bit DSP RISC processors. We minimized the area of this ALU by allowing different operations to share several hardware blocks. Moreover, we applied DFT(Design for Testability) to ALU and offered Bist(Built-In Self-Test) function. BIST is composed of pattern generation and response analysis. We used the reseeding method and testability design for the high fault coverage. These techniques reduce the test length. Chip's reliability is improved by testing and the cost of testing system can be reduced.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.59-70
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• 1993

An efficient test method based on march test is presented to cover line leakage failures associated with bit and word lines or mega bit DRAM chips. A modified column march (Y-march) pattern is derived to improve fault coverage against the data retention failure. Time delay concept is introduced to develop a new column march test algorithm detecting various data retention failures. A built-in test circuit based on the column march pattern is designed and verified using logic simulation, confirming correct test operations.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2832-2839
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• 1997

In this paper, a testing architecture and procedure that an idle ATM virtual channel can be utilized for TCP channel is proposed. Four kinds or methodologies for protocol conformance testing have been standardized in ISO. Remote testing method used popularly have some disadvantages that developer must operate system manually in case of System Under Test (SUT) active testing and we cannot control and observe Implementation Under Test (IUT) often. It is proper to adopt distribute testing method than remote test in order to maximize test coverage and optimize fault coverage for conformance testing in ATM systems, and it is required that TCP channel is prepared for distribute testing method. The proposed architecture can adopt distributed testing method without extra physical channel for testing control. Also we can maximize the test coverage and implement the automation of testing without intervention of operator sustaining normal operation of ATM equipment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.85-97
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• 2002

STUMPS has been widely used for built-in self-test of scan design with multiple scan chains. In the STUMPS architecture, there is very high correlation between the bit sequences in the adjacent scan chains. This correlation causes circuits lower the fault coverage. In order to solve this problem, an extra combinational circuit block(phase shifter) is placed between the LFSR and the inputs of STUMPS architecture despite the hardware overhead increase. This paper introduces an efficient test pattern generation technique and built-in self-test architecture for sequential circuits with multiple scan chains. The proposed test pattern generator is not used the input of LFSR and phase shifter, hence hardware overhead can be reduced and sufficiently high fault coverage is obtained. Only several XOR gates in each scan chain are required to modify the circuit for the scan BIST, so that the design is very simple.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.51-63
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• 1993

"Algorithm DA" is proposed to test linked 2-CFs(2-Coupling Faults) with order 2 or 3 which are not perfectly detected in conventional algorithms. "Test 1*", "Test 2*" and "Algorithm RA" are proposed restricted 3-CFS. The time complexity of "Test 1*" is reduced in view of the detection of 3-CFS. "Test 2*" and "Algorithm RA" have not only the reduces time complexity but also the improved fault coverage in comparison with conventional algorithms. And "Algorithm RA" can be applied step by step according to the degree of the fault coverage. If "Algorithm RA" is applied to the memory with parallel test. its time complexity is reduced considerably. It is proved that the MT(March Test) with nonlinear address sequences can not detect perfectly the CFs more complex than linked 2-CFs with order 3.ss sequences can not detect perfectly the CFs more complex than linked 2-CFs with order 3.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.15-24
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• 2009

This paper proposes an effective low power BIST architecture using the pattern mapping method for 100% fault coverage and the transition freezing method for making high correlative low power patterns. When frozen patterns are applied to a circuit, it begins to find a great number of faults at first. However, patterns have limitations of achieving 100% fault coverage due to random pattern resistant faults. In this paper, those faults are covered by the pattern mapping method using the patterns generated by an ATPG and the useless patterns among frozen patterns. Throughout the scheme, we have reduced an amount of applied patterns and test time compared with the transition freezing method, which leads to low power dissipation.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.572-580
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• 1996

This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partialscan design is introduced to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node size of the state functions of a sequential circuit in their binary decision diagram representations. Experimental results on ISCAS'95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 or 80% scan FFs for sl423. However, test gener-ators based on the previous IPM method have not achieved 100% fault coverage for those circuits.

• Journal of Korea Multimedia Society
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• v.10 no.10
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• pp.1260-1270
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• 2007

Testing and diagnosis of analog circuits(or mixed-signal circuits) continue to be a hard task for test engineers and efficient test methodologies to solve these problems are needed. This paper proposes a novel analog circuits test technique using time slot specification (TSS) based built-in current sensors (BICS). A technique for location of a fault site and separation of fault type based on TSS is also presented. The proposed built-in current sensors and TSS technique has high testability, fault coverage and a capability to diagnose catastrophic faults and parametric faults in analog circuits. In order to reduce time complexity of test point insertion procedure, external output and power nodes are used for test points and the current sensors are implemented in the automatic test equipment(ATE). The digital output of BICS can be easily combined with built-in digital test modules for analog IC test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.292-301
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• 2001

IDDQ Testing is a very effective testing method to detect many kinds of physical defects occurred in CMOS VLSI circuits. In this paper, we consider the most commonly occurring bridging faults in current CMOS technologies and develop pattern generator for IDDQ testing using efficient IDDQ test algorithms. The complete set of bridging faults between every pair of all nodes(internal and external nodes) within circuit under test is assumed as target fault model. The merit of considering the complete bridging fault set is that layout information is not necessary. Implemented test pattern generator uses a new neighbor searching algorithm and fault collapsing schemes to achieve fast run time, high fault coverage, and compact test sets. Experimental results for ISCAS benchmark circuits demonstrate higher efficiency than those of previous methods.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.188-188
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• 1999

The embedded atom method (EAM) of Daw and Baskes as a semiempirical method, has been successfully applied to the fcc or nearly filled d-band transition metals due to its computational feasibility and its methodological simplicity. Then Baskes modified the EAM (MEAM) to include directional bonding and applied it to metals, semiconductors, and diatomic gases, all of which have different types of bondings. Here, we present a detailed study of the energetics of adsorption on the fcc(111) surfaces and binary system within the framework of MEAM. In adsorption on fcc(111) surfaces, there are two energetically favored sites, so called, fcc site and hcp site, which may trigger stacking fault in the growth of films and might switch growth mode between 3D growth and layer by layer growth. We scrutinized the role of the hcp sites, which would offer dynamic growth pathways although the dynamics are not yet clear within the limited experimental resolution. Featuring these transient motions in the atomic level should contribute to the understanding the growth mechanisms on fcc(111) surface. And we also applied MEAM for initial stage energetics at the Cr coverage of sub- monolayer on W(110). We hope that recently observed extraordinary growth behavior at the Cr coverage of 0.7 monolayer, self- organized nano-scale lines, can be resolved in this MEAM binary system calculation.