• Journal of Power Electronics
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• v.16 no.4
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• pp.1513-1525
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• 2016

Rapid and accurate phase synchronization is critical for the reliable control of grid-tied inverters. However, the commonly used software phase-locked loop methods do not always satisfy the need for high-speed and accurate phase synchronization under severe grid imbalance conditions. To address this problem, this study develops a novel open-loop phase locking scheme based on a synchronous reference frame. The proposed scheme is characterized by remarkable response speed, high accuracy, and easy implementation. It comprises three functional cascaded blocks: fast orthogonal signal generation block, fast fundamental-frequency positive sequence component construction block, and fast phase calculation block. The developed virtual orthogonal signal generation method in the first block, which is characterized by noise immunity and high accuracy, can effectively avoid approximation errors and noise amplification in a wide range of sampling frequencies. In the second block, which is the foundation for achieving fast phase synchronization within 3 ms, the fundamental-frequency positive sequence components of unsymmetrical grid voltages can be achieved with the developed orthogonal signal construction strategy and the symmetrical component method. The real-time grid phase can be consequently obtained in the third block, which is free from self-tuning closed-loop control and thus improves the dynamic performance of the proposed scheme. The proposed scheme is adaptive to severe unsymmetrical grid voltages with sudden changes in magnitude, phase, and/or frequency. Moreover, this scheme is able to eliminate phase errors induced by harmonics and random noise. The validity and utility of the proposed scheme are verified by the experimental results.

• The Journal of the Acoustical Society of Korea
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• v.41 no.2
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• pp.159-165
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• 2022

In this paper, a frame synchronization structure for the Binary Phase Shift Keying (BPSK) modulation method in underwater acoustic communication was proposed. The proposed frame synchronization structure is largely divided into two. First, the approximate position and frequency offset of the frame are obtained by non-coherent correlation and sliding Fast Fourier Transform (FFT) method. Second, after compensating for the frequency error to the received signal, the exact position of the frame is obtained by coherent correlation method. Maritime experiments were conducted to confirm the performance of the 2-STEP frame synchronization structure. It was showed that the limitations of the non-coherent correlation and sliding FFT method can be verified when the power of the received signal was greatly reduced due to the channel characteristics. As a result, stable frame synchronization could be obtained by compensating for the frequency error and then using the coherent correlation method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.1-13
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• 1995

In this paper, we evaluated the mean acquisition time and it's variance of the rapid synchronization system using the DMF(Digital Matched Filter) under the DS/CDMA system which uses the long period PN code. And we implemented the synchronization system that satisfies the specification demanded by the proposed EIA/TIA Interim Standard of Qualcomm Company. We showed that the state of the PN spreading code was estimated using the DMF(Digital Matched Filter) and then exact and fast chip synchronization could be achieved by the early-late tracking loop in the multiple channel environment. And we suggested the possibility that this synchronization system could be useful in the emerging digital cellular DS/CDMA system.

• Journal of Digital Contents Society
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• v.8 no.3
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• pp.385-391
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• 2007

In this paper, we propose a frequency synchronization algorithm for S-DMT cable modem, which is practicable to the next-generation high capacity upstream physical layer in HFC networks. Analyzing several viable frequency synchronization algorithms of multicarrier systems, we proposed an algorithm using predetermined training sequence of repeated pattern in preamble field and residual frequency offset compensation with pilot signals. We verified that the simulation results of the proposed algorithm in AWGN showed good performance and suitability to the S-DMT upstream cable modem for fast frequency synchronization.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.485-495
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• 2000

The parallel computer system that uses parallel program on the application such as a large scale business or complex operation is required. One of crucial operation of parallel computer system is synchronization. A representative method of synchronization is barrier synchronization. A barrier forces all process to wait until all the process reach the barrier and then releases all of the processes. There are software schemes, hardware scheme, or combinations of these mechanism to achieve barrier synchronization which tends to use hardware scheme. Besides, barrier synchronization lets parallel computer system fast because it has fewer start-up overhead. In this paper, we propose a new switch module that can implement fast and fault-tolerant barrier synchronization in hardware scheme. A proposed barrier synchronization is operated not in full-switch-driven method but in processor-driven method. An effective barrier synchronization is executed with inexpensive hardware supports. Therefore, a new proposed hardware barrier synchronization is designed that it is operated in arbitrary network topology. In this paper, we only show comparison of barrier synchronization on Multistage Interconnection Network. This research results in 24.6-24.8% reduced average delay. Through this result, we can expect lower average delay in irregular network.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8B
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• pp.809-818
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• 2002

In this paper, we propose a fast cell search algorithm keeping compatible with the standard cell search algorithm of the WCDMA system. The proposed algorithm can acquire the synchronization of slot and frame times, and the code group identification using only one synchronization channel while the standard algorithm employs two synchronization channels called P-SCH and S-SCH. The proposed synchronization channel structure is the same as the P-SCH structure of the WCDMA system. However, the P-SCH is modulated with a specific polarization code, which is one element of new code group codes. The proposed algorithm can reduce both the BS' transmission power and the complexity of receiver as compared with the conventional one since only on synchronization channel is used. It is shown through the computer simulation that the proposed algorithm yields a significant improvement in terms of cell search time compared with the standard especially in low SNR environments.

• Journal of Korea Game Society
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• v.10 no.6
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• pp.147-155
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• 2010

On this paper, suggests a communication structure making possible to fast data send-receive for the gaming process synchronization. For these things, first of all, analyze the data send-receive speed effecting on the online game by the game genre. Moreover, we suggested a proper data communication structure like real-time online action game genre which gaming synchronization effects on the gaming process. Communication structure suggested on this paper is being used with TCP/UDP protocol, and it is applied to the network system and verify improved data send-receive speed. These data send-receive structure can be applied to the various online games.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.4
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• pp.234-242
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• 2010

Two-way ranging methods such as TWR and SDS-TWR have been considered for many ranging systems because these methods are useful in the absence of synchronization. To estimate the location of a mobile node, complicated ranging procedures consisting of ranging frames between an anchor node and the mobile node are performed. Supporting multiple mobile nodes such as a few hundreds or thousands and several anchor nodes, the ranging procedures have the fatal disadvantage of processing delay and inefficient traffic bandwidth. On the other hand, the one-way ranging method is simple and fast, but susceptible to network synchronization. In this paper, we propose a method to modify asynchronous ranging equations to establish exact frequency or frequency offset, a method to estimate frequencies or frequency offsets, and a method to establish post-facto synchronization with anchor nodes. The synchronization for a node pair is adapted using instantaneous time information and corresponding difference of distances can be determined. We evaluate the performance of TWR, SDS-TWR and proposed ranging algorithms.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.1
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• pp.72-80
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• 2015

In distributed generation systems, a grid-connected inverter should operate with synchronization to grid voltage. Considering that synchronization requires the phase angle of grid voltage, a phase locked loop (PLL) scheme is often used. The synchronous reference frame phase locked loop (SRF-PLL) is generally known to provide reasonable performance under ideal grid voltage. However, this scheme indicates performance degradation under the harmonic distorted or unbalanced grid voltage condition. To overcome this limitation, this paper proposes a phase and harmonic detection method of grid voltage using fast Fourier transform (FFT). To reduce the calculation time of FFT algorithm, minimum sampling data is taken from the voltage measurement to determine the phase angle and the magnitude of harmonic components. An experimental test setup for a grid-connected inverter system has been constructed. By comparative simulations and experiments under various abnormal grid voltage conditions, the proposed scheme has been proven to effectively track the phase angle of the grid voltage.