• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.199-203
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• 2013

In this paper, a fast algorithm of discrete cosine transform-based interpolation filter (DCT-IF) for HEVC (high efficiency video coding) encoder is proposed. DCT-IF filter accounts for around 30% of encoder complexity, according to the computational complexity analysis with the HEVC reference software. In this work, the proposed DCT-IF is optimized by applying frame-level interpolation, SIMD optimization, and task-level parallelization via OpenMP on a developed C-based HEVC encoder. Performance analysis is conducted by measuring speed-up factor of the proposed optimization technique on the developed encoder. The results show that speed-up factors by frame-level interpolation, SIMD, and OpenMP are approximately 38-46, 3.6-4.4, and 3.0-3.7, respectively. In the end, we achieved the speed-up factor of 498.4 with the proposed fast algorithm.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.582-590
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• 2010

he rate-distortion optimization (RDO) method in the H.264/AVC encoder is a technology that improves the coding efficiency, but increases the computational complexity. In this paper, a fast Intra mode decision algorithm using DCT (Discrete Cosine Transform) coefficients distribution is proposed to reduce the H.264 encoder complexity. The proposed method reduces the encoder complexity on average 68.40%, while the coding efficiency is slightly decreased compared with the H.264/AVC encoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.64-68
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• 2005

Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.

• Journal of Broadcast Engineering
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• v.21 no.2
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• pp.140-148
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• 2016

HEVC(High Efficient Video Coding) has twice times better compression ratio than H.264/AVC, but since the computational complexity has significantly increased in the encoder side, it may cause difficulty in real-time SW implementation in the encoder side. This paper proposes two methods about fast intra prediction. First, fast mode and prediction unit decision method using transform coefficients of the original block is proposed. and second, fast prediction unit decision method using coded block flag(cbf) is proposed. The proposed method achieves 42% encoder speed up with 0.8% bitrate increase compared with HM16.0.

• Journal of Broadcast Engineering
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• v.17 no.6
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• pp.1091-1105
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• 2012

In this paper, we analyzed statistical characteristics and complexity of HEVC encoder as a leading research of acceleration, optimization and parallelization. Computational complexity of the HEVC encoder is approximately twice the compression performance compared to H.264/AVC. But, the increase of encoder complexity remains a problem to be solved in the future. Before performing the research on acceleration, optimization and parallelization to reduce high complexity of HEVC encoder, we measure the complexity each module for HEVC encoder using it's reference software HM 7.1. We also measured the predicted complexity of fast HEVC encoder software, used in real applications, using HM 7.1 applying fast encoding method. The complexity is measured in terms of the operating cycle of the encoder software under the common test sequences and conditions in the Windows PC environment. In addition, we analyze statistical characteristics of HEVC encoder software according to encoding structures and limitation using coded bitstreams.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.849-857
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• 2011

Gaming on demand(GOD) makes people enjoy games by encoding and transmitting game screen at a server side, and decoding the video at a client side. In this paper, we propose a fast game video encoder for multiple users over network with low-powered devices. In the proposed system, the computational complexity of game encoders is reduced by using scene descriptors, which consists of an object motion vector, global motion, and scene change. With additional information from game engines, the proposed encoder does not need to perform various complexity processes such as motion estimation and ratedistortion optimization. The motion estimation and rate-distortion optimization skipped by scene descriptors. We found that the proposed method improved 192 % in terms of FPS, compared with x264 software. With partial assembly code, we also improved coding speed by 86 % in terms of FPS. We found that the proposed fast encoder could encode over 60 FPS for real-time GOD applications.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.725-733
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• 2012

MPEG and VCEG have constituted a collaboration team called JCT-VC(Joint Collaborative Team on Video Coding) and have been developing the HEVC(High Efficiency Video Coding) standard. The next generation video coding standard HEVC shows higher compression rate compared with the H.264/AVC standard, but the encoder computational complexity of the HEVC encoder is significantly high. In order to reduce this computational complexity in the HEVC encoder, a fast prediction unit decision is proposed. The proposed fast prediction unit decision method reduces the encoder complexity by skipping the remaining prediction units if the current prediction unit does not have any non-zero quantized transform coefficient. The proposed method reduces the encoder computational complexity by 50.3% comparing with HM6.0 but it maintains the same level of coding efficiency.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.659-662
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• 1999

In this paper we implement MP3 encoder based on integer operations. To implement MP3 encoder presented in ［1］, floating-point operations are required. But we devise an MP3 encoding method which is based on integer operations. To verify the method presented in this paper, we implement MP3 encoder using ARM processor. In this paper we present the method to change floating point operations into integer operations, and the ARM assembly programming technique to implement fast MP3 encoder. The MP3 encoder implement using integer processor consumes less power than the encoder implemented using floating-point processor. So the encoder implemented in this paper is suitable lot portable applications which requires low power consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.943-946
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• 2006

XML is the most widely used document format by advantage that self-contained for platform. So, currently the most used among other document format. but XML appeared new problem that memory and transmission. And that be used in environment a request restriction memory and fast transmission as like mobile field. Although discussion of XML binarization is going on progress. And fast Infoset configuration using XML Information Set is receiving attention that a way to lower file size of hold down a existing usage. In this paper, we designed of module using fast Infoset and PER among ASN.1 Encoding Rule for XML binarization. And we implementation of encoder constructed interlace by stage of translation from XML into binary XML.