• Title/Summary/Keyword: Fast Recovery Algorithm

검색결과 55건 처리시간 0.024초

Single Pixel Compressive Camera for Fast Video Acquisition using Spatial Cluster Regularization

  • Peng, Yang;Liu, Yu;Lu, Kuiyan;Zhang, Maojun
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제12권11호
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    • pp.5481-5495
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    • 2018
  • Single pixel imaging technology has developed for years, however the video acquisition on the single pixel camera is not a well-studied problem in computer vision. This work proposes a new scheme for single pixel camera to acquire video data and a new regularization for robust signal recovery algorithm. The method establishes a single pixel video compressive sensing scheme to reconstruct the video clips in spatial domain by recovering the difference of the consecutive frames. Different from traditional data acquisition method works in transform domain, the proposed scheme reconstructs the video frames directly in spatial domain. At the same time, a new regularization called spatial cluster is introduced to improve the performance of signal reconstruction. The regularization derives from the observation that the nonzero coefficients often tend to be clustered in the difference of the consecutive video frames. We implement an experiment platform to illustrate the effectiveness of the proposed algorithm. Numerous experiments show the well performance of video acquisition and frame reconstruction on single pixel camera.

An Efficient Coordinator Election Algorithm in Synchronous Distributed Systems (동기적 분산 시스템에서 효율적인 조정자 선출 알고리즘)

  • 박성훈
    • Journal of KIISE:Computer Systems and Theory
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    • 제31권10호
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    • pp.553-561
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    • 2004
  • Leader election is an important problem in developing fault-tolerant distributed systems. As a classic solution for leader election, there is Garcia-Molina's Bully Algorithm based on time-outs in synchronous systems. In this paper, we re-write the Bully Algorithm to use a failure detector instead of explicit time-outs. We show that this algorithm is more efficient than the Garcia-Molina's one in terms of the processing time. That is because the Bully_FD uses FD to know whether the process is up or down so fast and it speed up its execution time. Especially, where many processes are connected in the system and crash and recovery of processes are frequent, the Bully_FD algorithm is much more efficient than the classical Bully algorithm in terms of the processing time.

A Novel Technique for Tuning PI-Controllers in Induction Motor Drive Systems for Electric Vehicle Applications

  • Elwer Ayman Saber
    • Journal of Power Electronics
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    • 제6권4호
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    • pp.322-329
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    • 2006
  • In the last decade, the increasing restrictions imposed on the exhaust emissions from internal combustion engines and traffic limitations have increased the development of electrical propulsion systems for automotive applications. The goal of electrical and hybrid vehicles is the reduction of global emissions, which in turn leads to a decrease in fuel resource exploitation. This paper presents a novel approach for control of Induction Motors (IM) using the Particle Swarm Optimization (PSO) algorithm to optimize the parameters of the Proportional Integral Controller (PI-Controller). The overall system is simulated under various operating conditions. The use of PSO as an optimization algorithm makes the drive robust and insensitive to load variation with faster dynamic response and higher accuracy. The system is tested under variable operating conditions. The simulation results show a positive dynamic response with fast recovery time.

A Study on Digital Fault Locator for Transmission Line (송전선로용 디지털 고장점 표정장치에 관한 연구)

  • Lee, Kyung-Min;Park, Chul-Won
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • 제64권4호
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    • pp.291-296
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    • 2015
  • Transmission line is exposed to a large area, and then faults are likely to occur than the other component of power system. When a fault occurs on a transmission line, fault locator helps fast recovery of power supply on power system. This paper deals with the design of a digital fault locator for improvement accuracy of the fault distance estimation and a fault occurrence position for transmission line. The algorithm of a fault locator uses a DC offset removal filter and DFT filter. The algorithm utilizes a fault data of GPS time synchronized. The computed fault information is transmitted to the other side substation through communication. The digital fault locator includes MPU module, ADPU module, SIU module, and a power module. The MMI firmware and software of the fault locator was implemented.

Improved Performance of Permanent Magnet Synchronous Motor by using Particle Swarm Optimization Techniques

  • Elwer, A.S.;Wahsh, S.A.
    • Journal of Power Electronics
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    • 제9권2호
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    • pp.207-214
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    • 2009
  • This paper presents a modem approach for speed control of a PMSM using the Particle Swarm Optimization (PSO) algorithm to optimize the parameters of the PI-Controller. The overall system simulated under various operating conditions and an experimental setup is prepared. The use of PSO as an optimization algorithm makes the drive robust, with faster dynamic response, higher accuracy and insensitive to load variation. Comparison between different controllers is achieved, using a PI controller which is tuned by two methods, firstly manually and secondly using the PSO technique. The system is tested under variable operating conditions. Implementation of the experimental setup is done. The simulation results show good dynamic response with fast recovery time and good agreement with experimental controller.

A New Decision-Directed Carrier Recovery Algorithm (새로운 결정지향 반송파 복원 알고리즘)

  • 고성찬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • 제24권7A호
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    • pp.1028-1035
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    • 1999
  • To increase the throughput of data transmission in burst-mode TDMA communication systems and also to get a good BER performance at the same time, it is essential to rapidly acquire the carrier while keeping the desirable tracking performance. To achieve this goal, in this paper, a new decision-directed carrier recovery algorithm is presented. The proposed scheme does not incorporate the PLL and suppress the Gaussian random process of input noise by the pre-stage low pass filter so as to get both the fast acquisition and a good performance. Through computer simulations, the performance of the scheme is analyzed with respect to the acquisition time and bit error rate. The cycle slip in the proposed scheme is seldom observed at very low SNR environment in contrast to the previous proposed one. Because of this merit, it is not required to do the differential encoding and decoding in the proposed scheme.

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Extended ROHC Compression Algorithm for The Efficient Data Traffic Transmission in the IPv6 (차세대 IP체계에서 효율적인 데이터 전송을 위한 확장된 ROHC 알고리즘)

  • Kim Kyung-shin;Kang Moon-sik
    • Journal of the Korea Society of Computer and Information
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    • 제10권5호
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    • pp.187-198
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    • 2005
  • In this paper, we propose the enhanced header compression scheme for the efficient data traffic transmission in Ipv6 networks. The bandwidth of wireless links and IP networks will probably be limited due to properties of the physical medium and regulatory limits on the use of frequencies for radio communications. That is major cause of user throughput reduction. Therefore, We discuss the IPHC(RFC2507) and ROHC(RFC3095) scheme. IPHC is simple header compression scheme and ROHC is enhanced header compression that have fast optimal recovery scheme. We have studied the enhanced header compression scheme in ROHC. We will show that indication of compression context values preventing from packet losses can provide the fast recovery of compression state. Computer simulations show that the proposed scheme has better performance than the previous one.

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A Recovery Scheme of SSD-based Databases using Snapshot Log (스냅샷 로그를 사용한 SSD 기반 데이터베이스 복구 기법)

  • Lim, Seong-Chae
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • 제19권4호
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    • pp.85-91
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    • 2019
  • In this paper, we propose a new logging and recovery scheme that is suited for the high-performance transaction processing system base on flash memory storage. The proposed scheme is designed by considering flash's I/O characteristic of asymmetric costs between page update/read operations. That is, we substitute the costly update operation with writing and real-time usage of snapshot log, which is for the page-level physical redo. From this, we can avoid costly rewriting of a dirty page when it is evicted form a buffering pool. while supporting efficient revery procedure. The proposed scheme would be not lucrative in the case of HDD-based system. However, the proposed scheme offers the performance advance sush as a reduced number of updates and the fast system recovery time, in the case of flash storage such as SSD (solid state drive). Because the proposed scheme can easily be applied to existing systems by saving our snapshot records and ordinary log records together, our scheme can be used for improving the performance of upcoming SSD-based database systems through a tiny modification to existing REDO algorithms.

A Design of All-Digital QPSK Demodulator for High-Speed Wireless Transmission Systems (고속 무선 전송시스템을 위한 All-Digital QPSK 복조기의 설계)

  • 고성찬;정지원
    • Journal of Korea Society of Industrial Information Systems
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    • 제8권1호
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    • pp.83-91
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    • 2003
  • High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].

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Resilient Routing Protocol Scheme for 6LoWPAN (6LoWPAN에서 회복력 있는 라우팅 프로토콜 기법)

  • Woo, Yeon Kyung;Park, Jong Tae
    • Journal of the Institute of Electronics and Information Engineers
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    • 제50권11호
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    • pp.141-149
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    • 2013
  • IETF 6LoWPAN standard technique has been studied in IoT environment to support the IPv6 packet communication. 6LoWPAN protocol for transmission of packets mainly in the AODV routing protocol and a variety of extended techniques have been investigated. In particular, consisting of nodes with limited resources in a network error occurs when the 6LoWPAN reliable data transfer and fast routing method is needed. To this end, in this paper, we propose resilient routing protocol and extension of IETF LOAD algorithm, for optimal recovery path, More specifically, the optimal recovery path setup algorithm, signal flow, and detailed protocols for the verification of the reliability of packet transmission mathematical model is presented. The proposed protocol techniques to analyze the performance of the NS-3 performance through the simulation results that is end-to-end delay, throughput, packet delivery fraction and control packet overhead demonstrated excellence in comparison with existing LOAD.