• 한국멀티미디어학회논문지
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• 제22권5호
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• pp.527-534
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• 2019

Recently, Photo editing softwares such as digital cameras, Paintshop Pro, and Photoshop digital can create counterfeit images easily. Various techniques for detection of tamper images or forgery images have been proposed in the literature. A form of digital forgery is copy-move image forgery. Copy-move is one of the forgeries and is used wherever you need to cover a part of the image to add or remove information. Copy-move image forgery refers to copying a specific area of an image itself and pasting it into another area of the same image. The purpose of copy-move image forgery detection is to detect the same or very similar region image within the original image. In this paper, we proposed fast detection of forgery image using four step search based on discrete cosine transform and a four step search algorithm using discrete cosine transform (FSSDCT). The computational complexity of our algorithm reduced 34.23 % than conventional DCT three step search algorithm (DCTTSS).

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권6호
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• pp.2271-2288
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• 2015

The emerging high efficiency video coding (HEVC) standard adopts the quadtree-structured transform unit (TU) in the residual quadtree (RQT) coding. Each TU allows to be split into four equal sub-TUs recursively. The RQT coding is performed for all the possible transform depth levels to achieve the highest coding efficiency, but it requires a very high computational complexity for HEVC encoders. In order to reduce the computational complexity requested by the RQT coding, in this paper, we propose a fast TU size decision method incorporating an adaptive maximum transform depth determination (AMTD) algorithm and a full check skipping - early termination (FCS-ET) algorithm. Because the optimal transform depth level is highly content-dependent, it is not necessary to perform the RQT coding at all transform depth levels. By the AMTD algorithm, the maximum transform depth level is determined for current treeblock to skip those transform depth levels rarely used by its spatially adjacent treeblocks. Additionally, the FCS-ET algorithm is introduced to exploit the correlations of transform depth level between four sub-CUs generated by one coding unit (CU) quadtree partitioning. Experimental results demonstrate that the proposed overall algorithm significantly reduces on average 21% computational complexity while maintaining almost the same rate distortion (RD) performance as the HEVC test model reference software, HM 13.0.

• ETRI Journal
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• 제32권1호
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• 한국위성정보통신학회논문지
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• 제9권2호
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• pp.38-44
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• 2014

본 논문은 FMCW(Frequency Modulated Continuous Wave) 레이더 레벨 측정기 설계와 시뮬레이션을 통한 성능분석에 대하여 기술한다. 설계된 레벨미터는 FMCW radar를 이용하여 최대 20m 거리를 측정하며, 거리 계산을 위한 비트신호 분석기법으로 FFT(Fast Fourier Transform)와 Zoom-FFT를 적용하였다. 성능 분석을 위해 시뮬레이션을 통하여 두가지 기법을 비교 분석한 결과, 측정오류를 최소화하고 측정의 분해능을 향상시키기 위해서는 Zoom-FFT 기법이 보다 적절한 기법임을 확인하였다. 시뮬레이션은 주파수 분해능과 측정거리 분해능의 최적 값을 얻기 위해 다양한 조건에서 분석하였고, 1.024GHz 주파수 조건에서 2.2mm의 측정 분해능을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 D
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• pp.2184-2186
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• 2001

The research presented in this paper focuses on a method for the detection of High Impedance Fault(HIF). The method will use the fast wavelet transform and neural network system. HIF on the multi-grounded three-phase four-wires primary distribution power system cannot be detected effectively by existing over current sensing devices. These paper describes the application of fast wavelet transform to the various HIF data. These data were measured in actual 22.9kV distribution system. Wavelet transform analysis gives the frequency and time-scale information. The neural network system as a fault detector was trained to discriminate HIF from the normal status by a gradient descent method. The proposed method performed very well by proving the right state when it was applied staged fault data and normal load mimics HIF, such as arc-welder.

• 한국정보통신학회논문지
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• 제8권3호
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• pp.570-576
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• 2004

본 논문에서는 고속 무선 LAN에서 사용하는 IEEE 802.11a OFDM(Orthogonal Frequency Division Multiplexing)에서 주요 구성인 IFFT/FFT(Inverse Fast Fourier Transform/Fast Fourier Transform)에 대한 설계에 대해 비교하였다. 설계된 IFFT/FFT는 무선 LAN의 표준에 맞게 64 point의 FFT로 연산을 수행하며, S/P(Serial-to-Parallel)이나 P/S(Parallel-to-Serial)변환기가 필요 없는 Pipelined FFT의 구조로 설계하였다. 그 중 Radix-2 알고리즘을 이용한 R22SDF(Radix-2 Single-path Delay Feedback) 방식, R2SDF(Radix-2 Single-path Delay Feedback) 방식과 Radix-4 알고리즘을 이용한 R4SDF(Radix-4 Single-path Delay Feedback) 방식, R4SDC(Radix-4 Single-path Delay Commutator) 방식을 사용하여 비교하였다. 하드웨어 구현 시 발생하는 오차를 줄이기 위해 Butterfly 연산 후 일부 소수점을 가지고 계산하는 구조로 설계하였다. R22SDF 방식을 이용할 경우 메모리를 제외한 전체 게이트 수가 44,747 개로 다른 구조에 비해 적은 하드웨어와 낮은 오차율을 가진다.

• 한국멀티미디어학회논문지
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• 제16권4호
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• pp.411-417
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• 2013

In this paper, we proposed a fast detection method of copy-move forgery image based on low frequency coefficients of the DCT coefficients. We proposed a new matching criterion of copy-moved forgery image detection (MCD) using discrete cosine transform. For each $8{\times}8$ pixel block, the DCT transform is calculated. Our algorithm uses low frequency four (DC, 3 AC coefficient) and six coefficients (DC, 5 AC coefficients) of DCT per $8{\times}8$ pixel block. Our algorithm worked block matching for DCT coefficients of the $8{\times}8$ pixel block is slid by one pixel along the image from the upper left corner to the lower right corner. Our algorithm can reduce computational complexity more than conventional copy moved forgery detection algorithms.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.247-253
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• 2007

In this paper, a high throughput multiple transform architecture for H.264 Fidelity Range Extensions (FRExt) is proposed. New techniques are adopted which (1) regularize the $8{\times}8$ integer forward and inverse DCT transform matrices, (2) divide them into four $4{\times}4$ sub-matrices so that simple fast butterfly algorithm can be used, (3) because of the similarity of the sub-matrices, mixed butterflies are proposed that all the sub-matrices of $8{\times}8$ and matrices of $4{\times}4$ forward DCT (FDCT), inverse DCT (IDCT) and Hadamard transform can be merged together. Based on these techniques, a hardware architecture is realized which can achieve throughput of 1.488Gpixel/s when processing either $4{\times}4\;or\;8{\times}8$ transform. With such high throughput, the design can satisfy the critical requirement of the real-time multi-transform processing of High Definition (HD) applications such as High Definition DVD (HD-DVD) ($1920{\times}1080@60Hz$) in H.264/AVC FRExt. This work has been synthesized using Rohm 0.18um library. The design can work on a frequency of 93MHz and throughput of 1.488Gpixel/s with a cost of 56440 gates.

• 한국컴퓨터산업학회논문지
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• 제3권1호
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• pp.57-66
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• 2002

본 논문에서는 전류모드 CMOS의 기본회로를 이용해 다치 논리(Multiple-Valued Logic) 연산기를 설계하고자 한다. 우선, 2진(Binary)FFT(Fast Fourier Transform)를 확장해 다치 논리회로를 이용해서 고속 다치 FFT 연산기를 구현하였다. 다치 논리회로를 이용해서 구현한 FFT연산은 기존의 2치 FFT과 비교를 해 본 결과 상당히 트랜지스터의 수를 줄일 수 있으며 회로의 간단함을 알 수가 있었다. 또한, 캐리 전파 없는 가산기를 구현하기 위해서 ｛0,1,2,3｝의 불필요한(Redundant) 숫자 집합을 이용한 양의 수 표현을 FFT회로에 내부적으로 이용하여 결선의 감소와 VLSI 설계시 정규성과 규칙성으로 효과적이다. FFT승산을 위해서는 승산기의 연산시간과 면적을 다치 LUT(Look Up Table)로 이용해 승산의 역할을 하였다. 마지막으로 이진시스템(Bin system)과의 호환을 위해 다치 하이브리드형 FFT 프로세서를 제시하여 2진4치 부호기와 4치 2진 복호기 및 전류모드 CMOS회로를 사용하여 상호 호환성을 갖도록 설계를 하였다.

• 대한건축학회논문집:계획계
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• 제36권4호
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• pp.41-49
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• 2020

The purpose of this study was to investigate the use of the Deep Neural Networks(DNN) model to classify user's emotions, in particular Electroencephalography(EEG) toward Virtual-Reality(VR) based 3D design alternatives. Four different types of VR Space were constructed to measure a user's emotion and EEG was measured for each stimulus. In addition to the quantitative evaluation based on EEG data, a questionnaire was conducted to qualitatively check whether there is a difference between VR stimuli. As a result, there is a significant difference between plan types according to the normalized ranking method. Therefore, the value of the subjective questionnaire was used as labeling data and collected EEG data was used for a feature value in the DNN model. Google TensorFlow was used to build and train the model. The accuracy of the developed model was 98.9%, which is higher than in previous studies. This indicates that there is a possibility of VR and Fast Fourier Transform(FFT) processing would affect the accuracy of the model, which means that it is possible to classify a user's emotions toward VR based 3D design alternatives by measuring the EEG with this model.