• Journal of Korea Multimedia Society
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• v.22 no.5
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• pp.527-534
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• 2019

Recently, Photo editing softwares such as digital cameras, Paintshop Pro, and Photoshop digital can create counterfeit images easily. Various techniques for detection of tamper images or forgery images have been proposed in the literature. A form of digital forgery is copy-move image forgery. Copy-move is one of the forgeries and is used wherever you need to cover a part of the image to add or remove information. Copy-move image forgery refers to copying a specific area of an image itself and pasting it into another area of the same image. The purpose of copy-move image forgery detection is to detect the same or very similar region image within the original image. In this paper, we proposed fast detection of forgery image using four step search based on discrete cosine transform and a four step search algorithm using discrete cosine transform (FSSDCT). The computational complexity of our algorithm reduced 34.23 % than conventional DCT three step search algorithm (DCTTSS).

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.6
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• pp.2271-2288
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• 2015

The emerging high efficiency video coding (HEVC) standard adopts the quadtree-structured transform unit (TU) in the residual quadtree (RQT) coding. Each TU allows to be split into four equal sub-TUs recursively. The RQT coding is performed for all the possible transform depth levels to achieve the highest coding efficiency, but it requires a very high computational complexity for HEVC encoders. In order to reduce the computational complexity requested by the RQT coding, in this paper, we propose a fast TU size decision method incorporating an adaptive maximum transform depth determination (AMTD) algorithm and a full check skipping - early termination (FCS-ET) algorithm. Because the optimal transform depth level is highly content-dependent, it is not necessary to perform the RQT coding at all transform depth levels. By the AMTD algorithm, the maximum transform depth level is determined for current treeblock to skip those transform depth levels rarely used by its spatially adjacent treeblocks. Additionally, the FCS-ET algorithm is introduced to exploit the correlations of transform depth level between four sub-CUs generated by one coding unit (CU) quadtree partitioning. Experimental results demonstrate that the proposed overall algorithm significantly reduces on average 21% computational complexity while maintaining almost the same rate distortion (RD) performance as the HEVC test model reference software, HM 13.0.

• ETRI Journal
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• v.32 no.1
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.38-44
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• 2014

This paper presents design of a FMCW (Frequency Modulated Continuous Wave) level meter as well as simulation result of the designed system. The system is designed to measure maximum range of 20m since FMCW radar can be used for measuring short range distance. The distance is measured by analyzing the beat signal which is generated as result of mixing transmitting signal with the reflected received signal. The Fast Fourier Transform is applied to analyze the beat signal for calculating the displacement and Zoom FFT technique is used to minimize measurement error as well as increase the resolution of the measurement. The resolution of the measurement of the designed system in this paper is 2.2mm and bandwidth of 1.024GHz is used for simulation. Thus the simulation results are analyzed and compared in various conditions in order to get a comprehensive idea of frequency resolution and displacement resolution.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2184-2186
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• 2001

The research presented in this paper focuses on a method for the detection of High Impedance Fault(HIF). The method will use the fast wavelet transform and neural network system. HIF on the multi-grounded three-phase four-wires primary distribution power system cannot be detected effectively by existing over current sensing devices. These paper describes the application of fast wavelet transform to the various HIF data. These data were measured in actual 22.9kV distribution system. Wavelet transform analysis gives the frequency and time-scale information. The neural network system as a fault detector was trained to discriminate HIF from the normal status by a gradient descent method. The proposed method performed very well by proving the right state when it was applied staged fault data and normal load mimics HIF, such as arc-welder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.570-576
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• 2004

In this paper, we design the IFFT/FFT (Inverse fast Fourier Transform/Fast Fourier Transform) modules for IEEE 802.11a-1999, which is a standard of the High-speed Wireless LAN using the OFDM (Orthogonal Frequency Division Multiplexing). The designed IFFT/FFT is the 64-point FFT to be compatible with IEEE 802.11a and the pipelined architecture which needs neither serial-to-parallel nor parallel-to-serial converter. We compare four types of IFFT/FFT modules for the hardware complexity and operation : R22SDF (Radix-2 Single-path Delay feedback), the R2SDF (Radix-2 Single-path Delay feedback), R2SDF (Radix-4 Single-path Delay Feedback), and R4SDC (Radix-4 Single-path Delay Commutator). In order to minimize the error, we design the IFFT/FFT module to operate with additional decimal parts after butterfly operation. In case of the R22SDF, the IFFT/FFT module has 44,747 gate counts excluding RAMs and the minimized error rate as compared with other types. And we know that the R22SDF has a small hardware structure as compared with other types.

• Journal of Korea Multimedia Society
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• v.16 no.4
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• pp.411-417
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• 2013

In this paper, we proposed a fast detection method of copy-move forgery image based on low frequency coefficients of the DCT coefficients. We proposed a new matching criterion of copy-moved forgery image detection (MCD) using discrete cosine transform. For each $8{\times}8$ pixel block, the DCT transform is calculated. Our algorithm uses low frequency four (DC, 3 AC coefficient) and six coefficients (DC, 5 AC coefficients) of DCT per $8{\times}8$ pixel block. Our algorithm worked block matching for DCT coefficients of the $8{\times}8$ pixel block is slid by one pixel along the image from the upper left corner to the lower right corner. Our algorithm can reduce computational complexity more than conventional copy moved forgery detection algorithms.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.247-253
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• 2007

In this paper, a high throughput multiple transform architecture for H.264 Fidelity Range Extensions (FRExt) is proposed. New techniques are adopted which (1) regularize the $8{\times}8$ integer forward and inverse DCT transform matrices, (2) divide them into four $4{\times}4$ sub-matrices so that simple fast butterfly algorithm can be used, (3) because of the similarity of the sub-matrices, mixed butterflies are proposed that all the sub-matrices of $8{\times}8$ and matrices of $4{\times}4$ forward DCT (FDCT), inverse DCT (IDCT) and Hadamard transform can be merged together. Based on these techniques, a hardware architecture is realized which can achieve throughput of 1.488Gpixel/s when processing either $4{\times}4\;or\;8{\times}8$ transform. With such high throughput, the design can satisfy the critical requirement of the real-time multi-transform processing of High Definition (HD) applications such as High Definition DVD (HD-DVD) ($1920{\times}1080@60Hz$) in H.264/AVC FRExt. This work has been synthesized using Rohm 0.18um library. The design can work on a frequency of 93MHz and throughput of 1.488Gpixel/s with a cost of 56440 gates.

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.36 no.4
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• pp.41-49
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• 2020

The purpose of this study was to investigate the use of the Deep Neural Networks(DNN) model to classify user's emotions, in particular Electroencephalography(EEG) toward Virtual-Reality(VR) based 3D design alternatives. Four different types of VR Space were constructed to measure a user's emotion and EEG was measured for each stimulus. In addition to the quantitative evaluation based on EEG data, a questionnaire was conducted to qualitatively check whether there is a difference between VR stimuli. As a result, there is a significant difference between plan types according to the normalized ranking method. Therefore, the value of the subjective questionnaire was used as labeling data and collected EEG data was used for a feature value in the DNN model. Google TensorFlow was used to build and train the model. The accuracy of the developed model was 98.9%, which is higher than in previous studies. This indicates that there is a possibility of VR and Fast Fourier Transform(FFT) processing would affect the accuracy of the model, which means that it is possible to classify a user's emotions toward VR based 3D design alternatives by measuring the EEG with this model.