• Journal of the Korea Society of Computer and Information
• /
• v.3 no.2
• /
• pp.119-124
• /
• 1998

Block Matching Motion Estimation(BMME) Algorithm is demands a very large amount of computing power and have been proposed many fast algorithms. These algorithms are many problem that larger size of VLSI scale due to non-localized search block data and problem of non-reuse of input data for each processing step. In this paper, we designed systolic arry of high processing capacity, constraints input output pin size and reuse of input data for small VLSI size. The proposed systolic array is optimized memory access time because of iterative reuse of input data on search block and become independent of problem size due to increase of algorithm's parallelism and total processing elements connection is localized spatial and temporal. The designed systolic array is reduced O(N6) time complexity to O(N3) on moving vector and has O(N) input/output pin size.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.9A
• /
• pp.1392-1400
• /
• 1999

In this paper, we propose a two-stage fast full search algorithm for block motion estimation that produces the same performance to that of full search algorithm (FSA) but with remarkable computation reduction. The proposed algorithm uses the search region subsampling and the difference of adjacent pixels in the current block. In the first stage, we subsample the search region by a factor of 9, and then calculate mean absolute error (MAE) at the subsampled search points. And in the second stage, we reduce the search points that need block matching process by using the lower bound of MAE value at each search Point. We Set the lower bound of MAE value for each search point from the MAE values which are calculated at the first stage and the difference of adjacent pixels in the current block. The experimental results show that we can reduce the computational complexity considerably without any degradation of picture quality.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.3
• /
• pp.405-417
• /
• 2001

In this paper, since we currently using surveillance system of analog type bring about waste of resource and efficiency deterioration problems, we describe new solution that design and implementation to the digital surveillance system of new type applying compression techniques and encoding techniques of image data using MPEG-2 international standard. Also, we proposed fast motion estimation algorithm requires much less than the convectional digital surveillance camera system. In this paper a fast motion estimation algorithm is proposed the MPEG-2 video encoding. This algorithm is based on a hybrid use of the block matching technique and gradient technique. Also, we describe a method of moving object extraction directly using MPEG-2 video data. Since proposed method is very simple and requires much less computational power than the conventional object detection methods. In this paper we don't use specific H/W and this system is possible only software encoding, decoding and transmission real-time for image data.

• Journal of Broadcast Engineering
• /
• v.5 no.2
• /
• pp.247-259
• /
• 2000

This paper introduces a new technique that reduces the search times and Improves the accuracy of motion estimation using high temporal and spatial correlation of motion vector. Instead of using the fixed first search Point of previously proposed search algorithms, the proposed method finds more accurate first search point as to compensating searching area using high temporal and spatial correlation of motion vector. Therefore, the main idea of proposed method is to find first search point to improve the performance of motion estimation and reduce the search times. The proposed method utilizes the direction of the same coordinate block of the previous frame compared with a block of the current frame to use temporal correlation and the direction of the adjacent blocks of the current frame to use spatial correlation. Based on these directions, we compute the first search point. We search the motion vector in the middle of computed first search point with two fixed search patterns. Using that idea, an efficient adaptive predicted direction search algorithm (APDSA) for block matching motion estimation is proposed. In the experimental results show that the PSNR values are improved up to the 3.6dB as depend on the Image sequences and advanced about 1.7dB on an average. The results of the comparison show that the performance of the proposed APDSA algorithm is better than those of other fast search algorithms whether the image sequence contains fast or slow motion, and is similar to the performance of the FS (Full Search) algorithm. Simulation results also show that the performance of the APDSA scheme gives better subjective picture quality than the other fast search algorithms and is closer to that of the FS algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.5 no.11
• /
• pp.2191-2203
• /
• 2011

In this paper, we propose a fast and robust algorithm for fighting behavior detection based on Motion Vectors (MV), in order to solve the problem of low speed and weak robustness in traditional fighting behavior detection. Firstly, we analyze the characteristics of fighting scenes and activities, and then use motion estimation algorithm based on block-matching to calculate MV of motion regions. Secondly, we extract features from magnitudes and directions of MV, and normalize these features by using Joint Gaussian Membership Function, and then fuse these features by using weighted arithmetic average method. Finally, we present the conception of Average Maximum Violence Index (AMVI) to judge the fighting behavior in surveillance scenes. Experiments show that the new algorithm achieves high speed and strong robustness for fighting behavior detection in surveillance scenes.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.717-720
• /
• 1998

In this paper, we propose a VLSI architecture for implementing a crecently proposed fast block matching algorithm, which is called the HSBMA3S. The proposed architecture consists of a systolic array based basic unit and two shift register arrays. And it covers a search range of -32 ~+31. By using a basic unit repeatedly, we can redcue the number of gates. To implement the basic unit, we can select one among various conventional systolic arrays by trading-off between speed and hardware cost. In this paper, the architecture for the basic unit is selected so that the hardware cost can be minimized. The proposed architecture is fast enough for low bit-rate applications (frame size of 352x288, 30 frames/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic unit, the architecture can be used for the higher bit-rate application of the frame size of 720*480 and 30 frames/sec.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.10 no.5
• /
• pp.13-20
• /
• 2010

We proposed a new technique to perform fast video stabilization using integral image in this article. In the proposed technique, it evaluate local and global motion by the block matching using the generated integral image for each frame and compensate the motion like jitter. We made the various experimental jitter patterns to evaluate the effectiveness of the proposed technique and evaluated stabilization capability and execution time with the existing ones. Through the experiment, we found that the execution time of proposed technique was faster than that of existing techniques and the compensation of jitter was well done.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.3C
• /
• pp.278-286
• /
• 2010

Motion Compensated Frame Interpolation(MCFI) has been used to reduce motion jerkiness for dynamic scenes and motion blurriness for LCD-panel display as post processing for large screen and full HD(high definition) display. Conventionally, block matching algorithms (BMA) are widely used to do motion estimation for simplicity of implementation. However, there are still several drawbacks. So in this paper, we propose a novel shape-based ME algorithm to increase accuracy and reduce ME computational cost. To increase ME accuracy, we do motion estimation based on shape of moving objects. And only moving areas are included for motion estimation to reduce computational cost. The results show that the computational cost is 25 % lower than full search BMA, while the performance is similar or is better, especially in the fast moving region.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.43 no.4 s.310
• /
• pp.55-65
• /
• 2006

Most of fast block motion estimation algorithms reported so far in literatures aim to reduce the computation in terms of the number of search points, thus do not fit well with multimedia processors due to their irregular data flow. For multimedia processors, proper reuse of data is more important than reducing number of absolute difference operations because the execution cycle performance strongly depends on the number of off-chip memory access. Therefore, in this paper, we propose a Hexagon-shape line search (HEXSLS) algorithm using line search pattern which can increase data reuse from on-chip local buffer, and check sub-sampling points in line search pattern to reduce unnecessary SAD operation. Our experimental results show that the prediction error (MAE) performance of the proposed HEXSLS is similar to that of the full search block matching algorithm (FSBMA), while compared with the hexagon-based search (HEXBS), the HEXSLS outperforms. Also the proposed HEXSLS requires much lesser off-chip memory access than the conventional fast motion estimation algorithm such as the hexagon-based search (HEXBS) and the predictive line search (PLS). As a result, the proposed HEXSLS algorithm requires smaller number of execution cycles on media processor.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.7
• /
• pp.53-60
• /
• 2009

Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.