• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.405-413
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• 2013

In this paper, a high-reliability differential paired 24-bit eFuse OTP memory with program-verify-read mode for PMICs is designed. In the proposed program-verify-read mode, the eFuse OTP memory can do a sensing margin test with a variable pull-up load in consideration of programmed eFuse resistance variation and can output a comparison result through a PFb (pass fail bar) pin by comparing a programmed datum with its read one. It is verified by simulation results that the sensing resistance is lower with $4k{\Omega}$ in case of the designed differential paired eFuse OTP memory than $50k{\Omega}$ in case of its dual-port eFuse OTP memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1455-1462
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• 2012

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.7
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• pp.575-580
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• 2007

A 16 Mb 1T1C FeRAM device was integrated with BLT capacitors. But a lot of cells were failed randomly during the measuring the bit-line signal distribution of each cell. The reason was revealed that the grain size and orientation of the BLT thin film were severely non-uniform. And the grain size and orientation were severely affected by the process conditions of post heat treatment, especially nucleation step. The optimized annealing temperature at the nucleation step was $560^{\circ}C$. The microstructure of the BLT thin film was also varied by the annealing time at the step. The longer process time showed the finer grain size. Therefore, the uniformity of the grain size and orientation could be improved by changing the process conditions of the nucleation step. The FeRAM device without random bit-fail cell was successfully fabricated with the optimized BLT capacitor and the sensing margin in bit-line signal distribution of it was about 340 mV.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.611-614
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• 2002

In this paper, a novel error concealment, algorithm is proposed for the MPEG-4 video decoding. Apart from existing algorithms which fail to exhibit stable performance over various video sequences and error patterns, the proposed algorithm adopts a new hybrid scheme, which can achieve a consistent performance with reduced computational complexity. This algorithm is implemented on the basis of the MPEG-4 decoder, and the experimental results demonstrate that the new approach provides acceptable performance both subjectively and objectively at various bit error rates and video sequences.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.3
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• pp.267-274
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• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• Journal of the Korea Society for Simulation
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• v.11 no.3
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• pp.49-58
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• 2002

It takes 2 or 3 months to manufacture memory device. Defect has to exist owing to hundreds of processes. If there are too many defects, the memory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is needed for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The equipment development company had provided the redundancy analysis and each development company had developed and provided separately. So, to analyze the similar type of defects, redundancy analysis time can be very different by the manufacture. The purpose of this research is to strengthen the competitive price and to apply correlation concept in business for reducing the redundancy analysis time to repair the defects

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.365-375
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• 2014

This paper proposes an abnormal V-shaped-error-free non-blind deconvolution technique featuring an adaptively segmented forward-problem based iterative deconvolution (ASDCN) process. Unlike the algebraic based inverse operations, this eliminates any operations of differential and division by zero to successfully circumvent the issue on the abnormal V-shaped error. This effectiveness has been demonstrated for the first time with applying to a real analysis for the effects of the Random Telegraph Noise (RTN) and/or Random Dopant Fluctuation (RDF) on the overall SRAM margin variations. It has been shown that the proposed ASDCN technique can reduce its relative errors of RTN deconvolution by $10^{13}$ to $10^{15}$ fold, which are good enough for avoiding the abnormal ringing errors in the RTN deconvolution process. This enables to suppress the cdf error of the convolution of the RTN with the RDF (i.e., fail-bit-count error) to $1/10^{10}$ error for the conventional algorithm.

• Journal of Sensor Science and Technology
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• v.27 no.2
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• pp.126-131
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• 2018

Unlike the hydraulic power steering (HPS) system, which operates by the high pressure of a fluid obtained from the engine power, the motor-driven power steering (MDPS) system uses an electric motor to steer the wheel without consuming engine power. To steer the wheel with an electric motor, a worm wheel and a worm gear rotating between the steering shaft and motor are required. Any imperfection during the construction of an MDPS system or in a composing part creates noise and vibration, which can be sensed by a driver. To solve the noise and vibration problems, each part must be designed to not resonate with other parts. In this work, we developed the measurement and analysis systems to obtain the noise and the vibration of an automobile MDPS system. A signal analyzer was equipped with a 96 kHz, 24-bit ADC and a 150 MHz digital signal processor. The predetermined threshold value of the vibration in the MDPS system was used to determine the pass/fail, and the results were displayed on the screen. Our system can be used in the fabrication line to swiftly determine any imperfections in the MDPS system construction.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.15-19
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• 2011

The performance of the DRAM is strongly dependent on the purity and surface roughness of the TIT (TiN/Insulator/ TiN) capacitor electrodes. Hence, in the present study, we evaluate the effects of organic contamination and change of surface roughness on the cylindrical TIT capacitor electrodes during the wet cleaning process by various analytical techniques such as TDMS, AFM, XRD and V-SEM. Once the sacrificial oxide and PR (Photo Resist) are removed by HF, the organic contamination and surface oxide films on the bottom Ti/TiN electrode become visible. With prolonged HF process, the surface roughness of the electrode is increased, whereas the amount of oxidized Ti/TiN is reduced due to the HF chemicals. In the 80nm DRAM device fabrication, the organic contamination of the cylindrical TIT capacitor may cause defects like SBD (Storage node Bridge Defect). The SBD fail bit portion is increased as the surface roughness is increased by HF chemicals reactions.

• Proceedings of the KOSOMBE Conference
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• v.1996 no.05
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• pp.179-183
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• 1996

Most of the conventional electrocardiogaphies fail to detect signals other than P-QRS-T due to the limited SNR and bandwidth. High-resolution electrocardiography (HRECG) provides better SNR and wider bandwidth for the detection of micro-potentials with higher frequency components such as ventricual late potentials(LP). In this paper, we developed a HRECG using uncorrected XYZ lead. The overall gain of the amplifier is 4000 and the bandwidth is $0.5{\sim}300Hz$ without using 60Hz notch filter. Three 16-bit AH converters sample X, Y, and Z signals simultaneously with a sampling frequency of 2000Hz. Sampled data are transmitted to PC via a DMA-controlled serial communication channel using RS-485 and HDLC protocol. The noise level of the developed HRECG is less than $5{\mu}V_{rms,\;RTI}$. In order to further reduce the noise level, signal averaging technique is implemented utilizing template matching method. The SNR of the developed HRECG is high enough for the detection of LP.