• Journal of the Korea Society for Simulation
• /
• v.14 no.1
• /
• pp.1-8
• /
• 2005

In the semiconductor manufacturing, yield enhancement is an urgent issue. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.703-706
• /
• 2003

Yield enhancement in semiconductor fabrication is important. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map, a new simple schema which facilitates the failure analysis.

• Journal of Korean Institute of Industrial Engineers
• /
• v.41 no.3
• /
• pp.267-274
• /
• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• Proceedings of the Korea Society for Simulation Conference
• /
• 2003.11a
• /
• pp.147-151
• /
• 2003

Yield enhancement in semiconductor fabrication is important. Even though DRAM yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form patterns, it is usually an indication for the identification of equipment problems or process variations. In this paper describes the techniques to automatically classify a failure pattern using a fail bit map.

• Journal of the Korea Society for Simulation
• /
• v.11 no.3
• /
• pp.49-58
• /
• 2002

It takes 2 or 3 months to manufacture memory device. Defect has to exist owing to hundreds of processes. If there are too many defects, the memory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is needed for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The equipment development company had provided the redundancy analysis and each development company had developed and provided separately. So, to analyze the similar type of defects, redundancy analysis time can be very different by the manufacture. The purpose of this research is to strengthen the competitive price and to apply correlation concept in business for reducing the redundancy analysis time to repair the defects