• Title/Summary/Keyword: FPGA-based controller

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Development of PC based Digital Controller of Ultrasonic Motor Using FPGA (FPGA를 이용한 초음파모터의 PC기반 디지털 제어기 개발)

  • Kim, Dong-Ok;Lee, Hwa-Chun;Song, Sung-Geun;Kim, Young-Dong;Lim, Young-Cheol;Park, Sung-Jun
    • The Transactions of the Korean Institute of Power Electronics
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    • v.12 no.6
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    • pp.500-509
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    • 2007
  • In this paper, we propose a novel pc-based 8-channel USB interface digital multi-controller (DMC) has capacity to be able to adjust ultrasonic motor's (USM's) the parameters-frequency, amplitude, phase difference using FPGA. The proposed DMC can control parameters directly by digital logic through a FPGA. Since it has counter circuit for rotary encoder to measure position and velocity of USM, the other separate circuits are unnecessary. Therefore, it could reduce the size of controller and the production cost. Finally, to verify the performance of proposed DMC, we tested the speed characteristic of two types USM with no-load as adjusting the parameters.

Design of an FPGA Based Controller for Delta Modulated Single-Phase Matrix Converters

  • Agarwal, Anshul;Agarwal, Vineeta
    • Journal of Power Electronics
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    • v.12 no.6
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    • pp.974-981
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    • 2012
  • A FPGA based delta modulated single phase matrix converter has been developed that may be used in both cyclo-converters and cyclo-inverters. This converter is ideal for variable speed electrical drives, induction heating, fluorescent lighting, ballasts and high frequency power supplies. The peripheral input-output and FPGA interfacing have been developed through Xilinx 9.2i, to generate delta modulated trigger pulses for the converter. The controller has been relieved of the time consuming computational task of PWM signal generation by implementing the method of trigger pulse generation in a FPGA by using Hardware Description Language VHDL in Xilinx. The trigger circuit has been tested qualitatively by observing various waveforms on an oscilloscope. The operation of the proposed system has been found to be satisfactory.

An Implementation of CAN Communication Interface using the Embedded Processor System based on FPGA (FPGA 기반의 임베디드 프로세서 시스템을 이용한 CAN 통신 인터페이스 구현)

  • Koo, Tae-Mook;Park, Young-Seak
    • Journal of the Institute of Convergence Signal Processing
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    • v.11 no.1
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    • pp.53-62
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    • 2010
  • Recently, various industrial embedded systems including vehicles controlled electronically are evolving to distributed multi-micro controller system. Accordingly, there is a need for standard CAN(Controller Area Network) protocol that ensures high stability and reliability of communication and is simple to construct object-oriented system with high control efficiency. CAN communication interface used general-purpose processor doesn't have many limitations in various application development because of fixed hardware architecture. This paper design and implement a CAN communication interface system based on FPGA. It is verified function and performance of system through monitoring communication with existing AT90CAN128 controller. Implemented CAN communication interface can be reused in development of application systems based on FPGA. And it provides low-cost, small-size and low-power design advantages.

Automatic tune parameter for digital PID controller based on FPGA

  • Tipsuwanporn, V.;Jitnaknan, P.;Gulpanich, S.;Numsomran, A.;Runghimmawan, T.
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1012-1015
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    • 2003
  • Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. The adjust parameter of PID to achieve best response of process which be using time and may be error if user are not expert. Nowadays this problem was solved by develop PID controller which can analysis and auto tune parameter are appropriate with process which used principle of Ziegler ? Nichols but it are expensive and designed for each task. Thus, this paper proposes auto tune PID based on FPGA by use principle of Dahlin which maximum overshoot not over 5 percentages and do not fine tuning again. It have performance in control process are neighboring controller in industrial and simple to use. Especially, It can use various process and low price. The auto tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. It was verified by control model of temperature control system.

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Design and Implementation of CAN IP using FPGA (FPGA를 이용한 CAN 통신 IP 설계 및 구현)

  • Son, Yeseul;Park, Jungkeun;Kang, Taesam
    • Journal of Institute of Control, Robotics and Systems
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    • v.22 no.8
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    • pp.671-677
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    • 2016
  • A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

FPGA based POS MPPT control for a small scale charging system of PV-nickel metal hydride battery (FPGA를 이용한 소형 태양광 발전 니켈 수소 전지 충전 시스템의 POS MPPT 제어)

  • Lee, Hyo-Geun;Seo, Hyo-Ryong;Kim, Gyeong-Hun;Park, Min-Won;Yu, In-Keun
    • Proceedings of the KIEE Conference
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    • 2011.07a
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    • pp.1306-1307
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    • 2011
  • Recently, the small scale photovoltaic (PV) electronic devices are drawing attention as the upcoming PV generation system. The PV system is commonly used in small scale PV applications such as LED lighting and cell phone. This paper proposes photovoltaic output sensorless (POS) maximum power point tracking (MPPT) control for a small scale charging system of PV-nickel metal hydride battery using field-programmable gate array (FPGA) controller. A converter is connected to a small scale PV cell and battery, and performs the POS MPPT at the battery terminal current instead of being at the PV cell output voltage and current. The FPGA controller and converter operate based on POS MPPT method. The experimental results show that the nickel metal hydride battery is charged by the maximum PV output power.

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FPGA based POS MPPT Control for a Small Scale Charging System of PV-nickel Metal Hydride Battery (FPGA를 이용한 소형 태양광 발전 니켈 수소 전지 충전 시스템의 POS MPPT 제어)

  • Lee, Hyo-Guen;Seo, Hyo-Ryong;Kim, Gyeong-Hun;Park, Min-Won;Yu, In-Keun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.1
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    • pp.80-84
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    • 2012
  • Recently, the small scale photovoltaic (PV) electronic devices are drawing attention as the upcoming PV generation system. The PV system is commonly used in small scale PV applications such as LED lighting and cell phone. This paper proposes photovoltaic output sensorless (POS) maximum power point tracking (MPPT) control for a small scale charging system of PV-nickel metal hydride battery using field-programmable gate array (FPGA) controller. A converter is connected to a small scale PV cell and battery, and performs the POS MPPT at the battery terminal current instead of being at the PV cell output voltage and current. The FPGA controller and converter operate based on POS MPPT method. The experimental results show that the nickel metal hydride battery is charged by the maximum PV output power.

Verification of an Autonomous Decentralized UPS System with Fast Transient Response Using a FPGA-Based Hardware Controller

  • Yokoyama, Tomoki;Doi, Nobuaki;Ishioka, Toshiya
    • Journal of Power Electronics
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    • v.9 no.3
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    • pp.507-515
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    • 2009
  • This paper proposes an autonomous decentralized control for a parallel connected uninterruptible power supply (UPS) system based on a fast power detection method using a FPGA based hardware controller for a single phase system. Each UPS unit detects only its output voltage and current without communications signal exchange and a quasi dq transformation method is applied to detect the phase and amplitude of the output voltage and the output current for the single phase system. Fast power detection can be achieved based on a quasi dq transformation, which results in a realization of very fast transient response under rapid load change. In the proposed method, the entire control system is implemented in one FPGA chip. Complicated calculations are assigned to hardware calculation logic, and the parallel processing circuit makes it possible to realize minimized calculation time. Also, an Nios II CPU core is implemented in the same FPGA chip, and the software can be applied for non-time critical calculations. Applying this control system, an autonomous decentralized UPS system with very fast transient response is realized. Feasibility and stable operation are confirmed by means of an experimental setup with three UPSs connected in parallel. Also, rapid load change is applied and excellent performance of the system is confirmed in terms of transient response and stability.

Implementation of Web Based Embedded Digital Frame Using Nios II Embedded Processor and ${\mu}Clinux$ (Nios II 임베디드 프로세서와 ${\mu}Clinux$를 이용한 웹기반 임베디드 디지털 액자 구현)

  • Jeong, Mun-Su;Yang, Heui-Hwan;Jeong, Je-Myung
    • Proceedings of the Korean Information Science Society Conference
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    • 2008.06d
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    • pp.327-331
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    • 2008
  • 본 논문에서는 ALtera Cyclone II FPGA와 VGA Controller, ISP1362 Host Controller, DM9000A Ethernet Controller를 사용하여 FPGA를 구성하고, ${\mu}Clinux$를 포팅하여 Nano-X 기반에서 JPEG 파일을 디스플레이 시키는 임베디드 디지털 액자를 구현한다. 구현한 시스템은 일반적인 마이크로프로세서를 사용하지 않고 Altera 사의 Cyclone II FPGA를 이용해 직접 프로세서를 설계하고, ISP1362 Host Controller를 이용하여 USB 드라이브를 인식하며, DM9000A를 통해 웹과 연결하여 웹서버로부터 전송되어진 JPEG 이미지를 Display 할 수 있도록 설계하였다.

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Embedded Hardware Implementation of an FPGA Based Nonlinear PID Controller for the ROBOKER Arm (ROBOKER 팔의 제어를 위한 FPGA 기반 비선형 제어기의 임베디드 하드웨어 구현)

  • Kim, Jeong-Seob;Jeon, Hyo-Won;Jung, Seul
    • Journal of Institute of Control, Robotics and Systems
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    • v.13 no.12
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    • pp.1153-1159
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    • 2007
  • This paper presents the hardware implementation of nonlinear PID controllers for the ROBOKER humanoid robot arms. To design the nonlinear PID controller on an FPGA chip, nonlinear functions as well as the conventional PID control algorithm have to be implemented by the hardware description language. Therefore, nonlinear functions such as trigonometric or exponential functions are designed on an FPGA chip. Simulation studies of the position control of humanoid arms are conducted and results are compared. Superior performances by the nonlinear PID controllers are confirmed when disturbances are present. Experiments of humanoid robot arm control tasks are conducted to confirm the performance of our hardware design and the simulation results.