• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.111-113
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• 2007

본 논문에서는 FPGA를 사용하여 진행파형 초음파 모 터의 2상 입력 전원 전압의 주파수, 위상차, 진폭 및 2 상간의 전압차 조절이 가능하고, 8대의 초음파 모터를 동 시에 제어할 수 있는 8채널 USB통신 PC기반 초음파 모터 디지털 제어기를 제안한다. 제안한 제어기는 FPGA를 이용 한 디지털 논리에 의해 출력을 발생하기 때문에 PC로부 터 직접 제어 명령을 입력 받아 각각의 파라미터를 실시 간으로 조절할 수 있을 뿐만 아니라, 둘 이상의 파라미터 를 동시에 조절이 가능하다. 또한, PC와의 인터페이스는 USB통신 방식을 채택하여 제어 명령의 전달속도 향상 및 플러그 앤 플러그 방식을 통해 데스크 탑 컴퓨터는 물론 휴대용 컴퓨터나 PDA와 같은 다양한 플랫폼에서 사용할 수 있도록 설계하였다. 또한, 초음파 모터의 속도 및 위치를 계측하기 위해 사용된 로터리 엔코더 카운터 회로를 FPGA회로에 내장시켜 카운터를 위한 별도의 회로 구성이나 장비 구입의 필요성을 배제하였다. 따라서, 생산 단가 및 부피를 현저히 감소시켰다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.8
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• pp.2366-2380
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• 2024

In this study, a high-speed template matching system is proposed for wafer-vision alignment. The proposed system is designed to rapidly locate markers in semiconductor equipment used for wafer-vision alignment. We optimized and implemented a template-matching algorithm for the high-speed processing of high-resolution wafer images. Owing to the simplicity of wafer markers, we removed unnecessary components in the algorithm and designed the system using a field-programmable gate array (FPGA) to implement high-speed processing. The hardware blocks were designed using the Xilinx ZCU104 board, and the pyramid and matching blocks were designed using programmable logic for accelerated operations. To validate the proposed system, we established a verification environment using stage equipment commonly used in industrial settings and reference-software-based validation frameworks. The output results from the FPGA were transmitted to the wafer-alignment controller for system verification. The proposed system reduced the data-processing time by approximately 30% and achieved a level of accuracy in detecting wafer markers that was comparable to that achieved by reference software, with minimal deviation. This system can be used to increase precision and productivity during semiconductor manufacturing processes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1289-1295
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• 2007

In this paper, we implemented high-performance concurrent control system which manages whole RF systems with digital type and communicates with remote station on both wire and wireless networking. It consists of FPGA (Field Programmable Gate Array) part which controls forward/reverse LPA (Linear Power Amplifier), forward/reverse LNA (Low Noise Amplifier), channel cut wire/wireless TCP/IP, etc, master microprocessor (AVR), which manages the whole control system, Slave microprocessor which communicates SA (Spectrum Analyzer) and observes frequency spectrum of each channel with the resolution of 5KHz, 10 channel card microprocessor which independently observes each channel card and sets frequency synthesizer in channel cut and other peripherals and logics. The whole system is divided to two parts of H/W (hardware) and S/W (software) considering operational efficiency and concurrency, and implementation and cost. H/W consists of FPGA and microprocessor. We expected the optimized operation through H/W and SW co-design and hybrid H/W architecture.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2266-2270
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• 2005

In this paper, an internet based control application for dynamical systems is implemented. This implementation is maily targeted for the part of advanced control education. Intelligent control algorithms are implemented in a PC so that a client can remotely access the PC to control a dynamical system through the internet. Neural network is used as an on-line intelligent controller. To have on-line learning and control capability, the reference compensation technique is implemented as intelligent control hardware of combining a DSP board and an FPGA chip. GUIs for a user are also developed for the user's convenience. Actual experiments of motion control of a DC motor have been conducted to show the performance of the intelligent control though the internet and the feasibility of advanced control education.

• Proceedings of the KIEE Conference
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• 2000.11b
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• pp.336-338
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• 2000

Recently many studies have been performed for variable speed control of induction motor. Direct Torque Control(DTC) is emerging technique for variable speed control of PWM inverter driven induction motor. DTC allows the direct control of stator flux and instantaneous torque through simple algorithm. In this paper ASIC design technique using VHDL is applied to DTC based speed control of induction motor. ASIC for DTC based speed control is designed through the description of coordinate transformation, speed controller stator flux and torque estimator, stator flux and torque controller, stator flux position detector. FSM(Finite State Machine) and inverter voltage switching vector. Finally the above system has been implemented on the FPGA (XC4052XL-PG411). Simulation and experiment has been performed to verify the performance of the designed ASTC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10b
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• pp.658-660
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• 2003

본 논문에서는 AMBA 기반의 FPD 시스템에 적용 가능한 콘트라스트 컨트롤러를 설계 및 구현하였다. 제안한 콘트라스트 컨트롤러 내부에는 AMBA의 인터페이스 spec을 준수한 AMBA AHB 컨트롤러와 콘트라스트조정 블록, 메모리 컨트롤러. FPD 컨트롤러가 내장되어있다. 구현한 알고리즘은 실시간 처리가 가능하며 콘트라스트의 범위를 조정하는 가중치를 가진 알고리즘으로 기준되는 값을 이용하여 콘트라스트의 효율적인 조정이 가능하다. 콘트라스트 컨트롤러는 VHDL로 설계하였으며 FPGA를 이용한 H/W를 구현하여 TFT-LCD panel에 디스플레이 하여 검증하였다.

• Journal of IKEEE
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• v.27 no.4
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• pp.524-530
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• 2023

This paper proposes an efficient algorithm to detect CAN (Controller Area Network) bus attack based on a lightweight CNN (Convolutional Neural Network), and an IDS(Intrusion Detection System) was designed, implemented, and verified with FPGA. Compared to conventional CNN-based IDS, the proposed IDS detects CAN bus attack on a frame-by-frame basis, enabling accurate and rapid response. Furthermore, the proposed IDS can significantly reduce hardware since it exploits only one convolutional layer, compared to conventional CNN-based IDS. Simulation and implementation results show that the proposed IDS effectively detects various attacks on the CAN bus.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.388-390
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• 2006

This paper presents a hybrid SoC design for phase detection of single tone signal. The designed hybrid SoC is composed of three functional blocks, i.e., an analog to digital converter module, a phase detection module and a controller module. A design of the controller module is based on a 16-bit RISC architecture. An I/O interface and an LCD control interface for transmission and display of phase measurement values are included in the design of the controller module. A design of the phase detector is based on a recursive sliding-DFT. The recursive architecture effectively reduces the gate numbers required in the implementation of the module. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The decimation filter is designed to give 98dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator- comb(CIC) filter and a 30-tab FIR filter in the decimation. The hybrid SoC is verified in FPGA and implemented in 0.35 CMOS Technology.