• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.30-35
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• 2009

In this paper, we propose the flexible design architecture for a continuous packet connectivity (CPC) Protocol among additional features of 3GPP HSPA+. In order to meet a practical intellectual property (IP) reuse and the developing time reduction design goals, we utterly take a CPC protocol into account to be realized by reusing digital signal processor (DSP) IP of the proven high speed packet access (HSPA) platform with the minimum hardware modification and addition. Based on the Teak series DSP, the proposed CPC protocol is divided into discontinuous transmit and receive mode, CPC manager, and interface with the proven HSPA platform. According to the regularized verification flow for wireless cellular communication applications, the proposed CPC protocol has been verified in various test scenarios.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.459-466
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• 2002

Modern embedded system employs a hybrid architecture which contains a general micro processor and reconfigurable devices such as FPGAS to retain flexibility and to meet timing constraints. It is a hard and important problem for embedded system designers to explore and find a right system configuration, which is known as design space exploration (DSE). With DES, it is possible to predict a final system configuration during the design phase before physical implementation. In this paper, we implement a timing analysis simulator for a DSE on a hybrid embedded system. The simulator, integrating exiting timing analysis tools for hardware and software, is designed by extending Y-chart approach, which allows quantitative performance analysis by varying design parameters. This timing analysis simulator is expected to reduce design time and costs and be used as a core module of a DSE for a hybrid embedded system.

• Journal of IKEEE
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• v.22 no.4
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• pp.901-906
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• 2018

Due to the development of display technologies for images, the resolution and quality of images are increasing day by day. In accordance with the development of the display technology, researches have been actively conducted on technologies for converting and displaying existing images to higher resolution and quality. Since the results of theses studies are included in the image signal processor, hardware implementation is indispensable. In this paper, we propose a real-time HDR(High Dynamic Range) conversion hardware implementation of LDR(Low Dynamic Range) image using luminance distribution. The proposed method extracts the features of the image using the histogram of the luminance distribution, and extends the luminance and color based on the extracted features. In addition, when the proposed method is designed by hardware IP(Intellectual Property) and its performance is verified, 4K DCI(Digital Cinema Image) can be handled at a rate of 30fps at 265.46MHz.