• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.9
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• pp.1560-1565
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• 2010

The renewable resource are getting more attentions with increased concerns on the depletion of fossil fuels and several environmental issues like emission problem. Wind power is a representative option among several renewable sources and the generation capacity using wind power is being increased. However, the wind generation is so volatile on its output characteristic, so it is required to assess the grid impact of wind power generation by measuring the fluctuation effect more precisely. This paper proposes the method for measuring the generation output according to IEC 61400-21(Measurement and assessment of power quality characteristics of grid connected wind turbines) to assess the power quality of wind turbine generation. In addition, it shows an application case to a small-scale wind power generator. In the case study, it suggests a structure design of the proposed measurement instrument both on hardware and software aspects, which is composed of a remote monitoring & data analysis program and an FPGA based real-time signal processing device.

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3C
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• pp.264-270
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• 2006

In this paper, we propose the modified display color control system using white point line, boundary lines and S-shaped curves to emphasize blue and red tone colors on CIE1931 diagram. The proposed system divides RGB gamut into movable area and non-movable area by using boundary lines. The colors in movable area are moved into right side or left side along quadratic curve to change the bluish (or reddish) color to more bluish (or more reddish), while those in non-movable area are excepted from color control to prevent skin color from changing. The loci of the quadratic curves are very similar to the arc of the white-point line which connects all points that represent the chromaticities of a black body radiator at different temperatures and is also called the black body locus. The RGB gamut extension by movement of chromaticity coordinate can improve color reproducibility. Therefore in the case of application to LCD, the display shows excellent performance because the LCD's color reproducibility is comparatively lower than that of other display systems. The proposed system is also experimentally demonstrated with Xilinx Virtex FPGA XCV2000E- 6BG560 and the TV set.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1787-1790
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• 2005

We have developed satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2) scheduled to be launched in 2007. The analog sun sensors which have been continuously developed since the 1990s are not adequate for satellites which require fine attitude control system. From the mission requirements of STSAT-2, a compact, fast and fine digital sensor was proposed. The test of the fine attitude determination for the pitch and roll axis, though the main mission of STSAT-2, will be performed by the newly developed FDSS. The FDSS use a CMOS image sensor and has an accuracy of less than 0.01degrees, an update rate of 20Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize the weight while maintaining sensor accuracy by a rigorous centroid algorithm. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA) in acquiring images from the CMOS sensor, and storing and processing the data. This paper also describes the analysis of the optical performance for the proper aperture selection and the most effective centroid algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.261-267
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• 2001

This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.105-113
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• 2004

This paper proposes 3D graphics accelerator, especially rendering unit, for portable devices. The existing 3D architecture is not suitable for portable devices because of its huge size. To reduce the size, we use iterative architecture and fixed-point calculation. In this paper, we suggest the format of fixed-point comparing with the result images, and some special technique to control. Finally, it is implemented with FPGA and 0.25um ASIC technology respectively. The ASIC chip can execute 47.88M pixels per second. The size of ASIC chip is 4.9287mm*4.9847mm and the power consumption is 263.7mW with 50MHz operation frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.558-567
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• 2003

Most digital signal processors provide 4 external interrupt input channels. But these are not sufficient for external interrupts of motor controls. Customized programmable interrupt controller, 8259, has 8 interrupt channels. Therefore, in the case of more external interrupt channels are needed, designers must expand by cascading the 8259. And this, 8259 device, have some inconvenience of interfacing the microprocessor in motor controls. In this paper, the expanded interrupt controller with 14 sufficient interrupt input channels for motor controls is designed using VHDL on the purpose of interfacing the microprocessor to the interrupt controller more compatibly and increasing the device utilization of FPGA/CPLD designed another peripherals. The interrupt controller model and each function blocks is proposed and illustrated. Simulation result are presented to estimate the designed interrupt controller.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.142-146
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• 2012

Today, the demand for high-speed data communication and mobile communication has exploded. Thus, there is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication with these characteristics consists of a master unit (MU) and a slave unit (SU). However, the digital optical units that are currently commercialized or being developed transmit data without compression. Thus, digital optical communication using these units is restricted by the quantity of optical frames when adding diversity or operating with various combinations of CDMA, WCDMA, WiBro, GSM, LTE, and other mobile communication technologies. This paper suggests the application of a data compression algorithm to a digital signal processor (DSP) chip as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD) of a digital optical unit to add separate optical waves or to transmit complex data without specific changes in design of the optical frame.