• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2141-2152
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• 1998

In this paper, we design and implement an indoor wireless modem using small signal of ISM band regulation, which can tranceive reliable data streams. We use direct sequence spead spectrum (DS-SS) signaling with synchronous BPSK and QPSK modulation, convolutional coding with viterbi decoding. The radio frequency module uses frequency devision duplexing in 900 MHz band, and the digital module is implemented with FPGAs for the purpose fo ASIC design. The perfomrance of our own acquistion and tracking circuit consisting digital matched filter and decision logic is proved by experiments, and the possibility of file transfer at indoor environment with the entrie system that the modem is connected the PC through RS-232C port is verified.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1147-1152
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• 2004

This paper presents the design of a multi-standard NTSC/PAL video encoder. The encoder converts International Telecommunication Union-Recommendation (ITU-R) BT.601 4:2:2, ITU-R BT.656 or RGB inputs from various video sources into National Television Standards Committee (NTSC) or phase-alternate line (PAL) TV signals in both S-video and composite video baseband signals (CVBS). The encoder adopts multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce high-quality digital video signals of 1 least significant bit (LSB) error or less. The proposed encode. is experimentally demonstrated by using the Altera APEX20K600EBC652-3 device.

• The KIPS Transactions:PartA
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• v.12A no.4 s.94
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• pp.313-320
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• 2005

The 2-D discrete cosine transform (DCT) is an integral part of video and image processing; it is used in both the PEG and MPEG enciding standards. As streaming video is brought to mobile devices, it becomes important that it is possible to calculate the DCT in an energy-efficient manner. In this paper, we present a new algorithm the DCT with a linear array PEs. This design is optimized for energy efficiency. We analyze the energy, area, and latency tradeoffs available with this design and then compare its energy dissipation, area, and latency to those of Xilinx's optimized IP core.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.366-373
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• 2007

In this paper we propose a multi-channel speech pickup system for calling quality enhancement of hands-free communication using ALTERA Nios-II processor. Multi-channel speech pickup system uses Delay-and-Sum beamformer with zero-padding interpolator. This paper implements speech pickup system using the Nios-II processor with real-time I/O data processing speed. The proposes speech pickup embedded system shows a good agreement with those of computer simulation(MATLAB) and conventional DSP processor(TMS320C6711) result. The proposed method is effective more than previous methods in cost and design processing time. As a result, LE(Logic Element) of hardware used 3,649/5,980(61%) on a chip.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.357-358
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• 2013

의학의 발달로 인해 전세계적으로 인구의 고령화가 진행되어 노인 인구가 차지하는 비중이 갈수록 증가하고 있다. 본 논문은 고령자를 위한 작품으로 카메라와 FPGA Board, Touch Panel을 유기적으로 결합하여 음악감상과 운동효과를 가져올 수 있는 게임을 포함한 하드웨어기반 시스템을 소개한다. 간단히 공을 화면에 맞추는 게임과 손 모양 인식에 따라 음악을 제어할 수 있는 부분의 설계와 알고리즘을 기술하고 있다. 본 시스템은 노인들에게 편리하고 간단한 UI를 제공하여 실내에서 여가 시간을 보낼 때 부담이 가지 않는 운동을 할 수 있는 게임을 하며 음악을 들으면서 건강증진, 치매예방 및 심신을 안정시킬 수 있다. 본 시스템은 평균 77% 이상 동작인식성공률을 가진다.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.4
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• pp.347-354
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• 2022

The synthetic aperture radar(SAR) is an equipment that can acquire images in all weathers day and night based on radar signals. The on-board processor of satellite SAR generates transmission signal by digital signal processing, converts it into an analog signal and transmits to antenna. Until the transmission signal generated by on-board processor is output, the signal passes the transmission cables and analog devices. At this time, these hardware distort the signal and makes SAR performance worse. To improve the performance, pre-distortion technique is used. But, general pre-distortion using taylor series is not sufficient to compensate for the distortion. This paper suggests transmit signal design method with improved pre-distortion. This paper uses envelop sampling method and interpolation filter for frequency domain compensation. The proposed method accurately compensates the hardware distortion and reduces resource usage of FPGA. To analyze proposed method's performance, IRF characteristics are compared when the proposed method applies to signal with errors.

• Journal of the Korean Society of Systems Engineering
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• v.17 no.2
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• pp.49-60
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• 2021

The Core Protection Calculator System (CPCS) is vital for plant safety as it ensures the required Specified Acceptance Fuel Design Limit (SAFDL) are not exceeded. The CPCS generates trip signals when Departure from Nucleate Boiling Ratio (DNBR) and Local Power Density (LPD) exceeds their predetermined setpoints. These setpoints are established based on the operating margin from the analysis that produces the SAFDL values. The goal of this research is to create a simplified CPCS that optimizes operating margin for I-SMRs. Because the I-SMR is compact in design, instrumentation placement is a challenge, as it is with Ex-core detectors and RCP instrumentation. The proposed CPCS addresses the issue of power flux measurement with In-Core Instrumentation (ICI), while flow measurement is handled with differential pressure transmitters between Steam Generators (SG). Simplification of CPCS is based on a Look-Up-Table (LUT) for determining the CEA groups' position. However, simplification brings approximations that result in a loss of operational margin, which necessitates compensation. Appropriate compensation is performed based on the result of analysis. FPGAs (Field Programmable Gate Arrays) are presented as a way to compensate for the inadequacies of current systems by providing faster execution speeds and a lower Common Cause Failure rate (CCF).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.33-40
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• 2005

This paper describes a design of FFT/IFFT Core(FFT256/2k), which is an essential block in terrestrial DMB modem. It has four operation modes including 256/512/1024/2048-point FFT/IFFT in order to support the Eureka-147 transmission modes. The hybrid architecture, which is composed of R2SDF and R2SDC structure, reduces memory by $62\%$ compared to R2SDC structure, and the SQNR performance is improved by TS_CBFP(Two Step Convergent Block Floating Point). Timing simulation results show that it can operate up to 50MHz(a)2.5-V, resulting that a 2048-point FFT/IFFT can be computed in 41-us. The FFT256/2k core designed in Verilog-HDL has about 68,400 gates and 58,130 RAM. The average power consumption estimated using switching activity is about 113-mW, and the total average SQNR of over 50-dB is achieved. The functionality of the core was fully verified by FPGA implementation.

• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.554-560
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• 2017

Accurate altimetry is required for the reliable flight control of drones or unmanned air vehicles (UAVs), and the radar altimeter is commonly used owing to its accuracy for the ground level. Due to the limitation for size, weight and power consumption, the frequency modulated continuous wave (FMCW) radar is appropriate for drone because it has lower complexity than that of pulse Doppler (PD) radar. Especially, fast-ramp FMCW radar, which transmits linear FM signal during very short period, is generally utilized, because it is robust for the ego-motion of drone. Therefore, we present the design and implementation results of the radar signal processor (RSP) for fast-ramp FMCW radar system. The proposed RSP was designed with Verilog-HDL and implemented with Altera Cyclone-IV FPGA device. Implementation results show that the proposed RSP includes 27,523 logic elements, 15,798 registers and memory of 138Kbits and can measure the altimeter at the rate of 100Hz with the operating frequency of 50MHz.