• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1553-1557
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• 2004

A real-time processing system for embedded hardware genetic algorithm is suggested. In order to operate basic module of genetic algorithm in parallel, such as selection, crossover, mutation and evaluation, dual processors based architecture is implemented. The system consists of two Xscale processors and two FPGA with evolvable hardware, which enables to process genetic algorithm efficiently by distributing the computational load of hardware genetic algorithm to each processors equally. The hardware genetic algorithm runs on Linux OS and the resulted chromosome is executed on evolvable hardware in FPGA. Furthermore, the suggested architecture can be extended easily for a couple of connected processors in serial, making it accelerate to compute a real-time hardware genetic algorithm. To investigate the effect of proposed approach, performance comparisons is experimented for an typical computation of genetic algorithm.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.145-151
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• 2015

We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.5
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• pp.55-63
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• 2007

This paper has investigated the susceptibility of an FPGA implementation of a block cipher against side channel analysis attacks. We have performed DPA attacks and DEMA attacks (in the nea. and far field) on an FPGA implementation of ARIA which has been implemented into two architectures of S-box. Although the number of needed traces for a successful attack is increased when compared with existing results on smart cards, we have shown that ARIA without countermeasures is indeed very susceptible to side channel analysis attacks regardless of an architecture of S-box.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.37-44
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• 2000

In this paper, an efficient hardware architecture of Lempel-Ziv compressor for real time data compression is proposed. The accumulated shift operations in the Lempel-Ziv algorithm are the major problem, because many shift operations are needed to prepare a dictionary buffer and matching symbols. A new efficient architecture for the fast processing of Lempel-Ziv algorithm is presented in this paper. In this architecture, the optimization technique for dictionary size, a new comparing method of multi symbol and a rotational FIFO structure are used to control shift operations easily. For the functional verification, this architecture was modeled by C programming language, and its operation was verified by running on commercial DSP processor. Also, the design of overall architecture in VHDL was synthesized on commercial FPGA chip. The result of critical path analysis shows that this architecture runs well at the input bit rate of 256kbps with 33MHz clock frequency.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.8
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• pp.2816-2830
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• 2022

Number Theoretic Transform (NTT) is a method to design efficient multiplier for large integer multiplication, which is widely used in cryptography and scientific computation. On top of that, it has also received wide attention from the research community to design efficient hardware architecture for large size RSA, fully homomorphic encryption, and lattice-based cryptography. Existing NTT hardware architecture reported in the literature are mainly designed based on radix-2 NTT, due to its small area consumption. However, NTT with larger radix (e.g., radix-4) may achieve faster speed performance in the expense of larger hardware resources. In this paper, we present the performance evaluation on NTT architecture in terms of hardware resource consumption and the latency, based on the proposed radix-2 and radix-4 technique. Our experimental results show that the 16-point radix-4 architecture is 2× faster than radix-2 architecture in expense of approximately 4× additional hardware. The proposed architecture can be extended to support the large integer multiplication in cryptography applications (e.g., RSA). The experimental results show that the proposed 3072-bit multiplier outperformed the best 3k-multiplier from Chen et al. [16] by 3.06%, but it also costs about 40% more LUTs and 77.8% more DSPs resources.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.381-384
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• 2006

PDP is watched as a wall-mounted flat displayer for merits, such as ability to visual maximize and natural color reproduction. But it is more necessary to research video quality why PDP is competing with another displayer. This paper is explaned HDL software architecture implementaion for PDP test-bed module and producing board using FPGA to research 42" PDP video quality.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.5
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• pp.521-524
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• 2015

This letter presents a selective wireless power transfer architecture using a reconfigurable multi-port amplifier. The proposed wireless power transfer architecture is composed of a phase shifter part controlled by FPGA, two class-E power amplifiers, a four-port power combiner and two coil loads. Depending on the phase control of FPGA, the power ratio of outputs at the two coil loads becomes 1:1, 2:0 and 0:2. The manufactured system has delivered 1W DC power to loads at 125 kHz. The total DC-to-DC conversion efficiency shows more than 40 % including PA efficiency of 79 %.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.1
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• pp.100-106
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• 2017

In this paper, we propose a parallel optimization method of Aho-Corasick (AC) algorithm and Parallel Failureless Aho-Corasick (PFAC) algorithm using Open Computing Language (OpenCL) on Field Programmable Gate Array (FPGA). The low throughput of string matching engine causes the performance degradation of network process. Recently, many researchers have studied the string matching engine using parallel computing. FPGA's vendors offer a parallel computing platform using OpenCL. In this paper, we apply the AC and PFAC algorithm on DE1-SoC board with Cyclone V FPGA, where the optimization that considers FPGA architecture is performed. Experiments are performed considering global id, local id, local memory, and loop unrolling optimizations using PFAC algorithm. The performance improvement using loop unrolling is 129 times greater than AC algorithm that not adopt loop unrolling. The performance improvements using loop unrolling are 1.1, 0.2, and 1.5 times greater than those using global id, local id, and local memory optimizations mentioned above.

• Smart Structures and Systems
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• v.3 no.1
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• pp.69-88
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• 2007

In this study, Field-Programmable Gate Arrays (FPGAs) are investigated as a practical solution to the challenge of designing an optimal platform for implementing algorithms in a wireless sensing unit for structuralhealth monitoring. Inherent advantages, such as tremendous processing power, coupled with reconfigurable and flexible architecture render FPGAs a prime candidate for the processing core in an optimal wireless sensor unit, especially when handling Digital Signal Processing (DSP) and system identification algorithms. This paper presents an effort to create a proof-of-concept unit, wherein an off-the-shelf FPGA development board, available at a price comparable to a microprocessor development board, was adopted. Data processing functions, including windowing, Fast Fourier Transform (FFT), and peak detection, were implemented in the FPGA using a Matlab Simulink-based high-level abstraction tool rather than hardware descriptive language. Simulations and laboratory tests were carried out to validate the design.