• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.5
• /
• pp.2680-2700
• /
• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• The Bulletin of The Korean Astronomical Society
• /
• v.36 no.2
• /
• pp.82.1-82.1
• /
• 2011

Korea Astronomy and Space Science Institute (KASI) operates 2 solar radio observing facilities, e-CALLISTO (Earthwide network of Compound Astronomical Low-cost Low-frequency Instrument for Transportable Observatory) station and Korean Solar Radio Burst Locator (KSRBL). Although e-CALLISTO tracking system improvement.is underway, at least 6 new events were observed in this year. Software development for KSRBL is in progress. The antenna calibration software was updated and flux calibration software was developed. Also the automatic daily overview spectrum monitoring system is now operational. We found solutions to several problems including spurious data and FPGA board communication. However, a few minor unsolved hardware problems still persist. Meanwhile, at least 6 new events were observed by KSRBL in this year, and a comparative study with HXR is currently underway.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.6
• /
• pp.1533-1545
• /
• 1996

In this paper, the design and implementation of echo canceller with new variable step size algorithm is discussed. The method used in the new algorithm is to periodically adopt the test function which helps an optimal coefficient tracking. This algorithm outperforms LMS and VS algorithms in convergence speed and steady state error. As the period of test function is decreased, the speed of convergence is improved, but the number of calculation is increased, then the trade off between these parameters must be considered. Simulation results show new algorithm outperforms LMS and VS algorithms in convergence rate. For the design of hardware, circuit is designed with VHDL, and synthesized with Act1 withc is a FPGA library of ActelTM in use of synovation of InterGraph$^{TM}$. Verification of the synthesized circuit is carried out with simulator DLAB. The circuit based on the algorithm which is suggested in this paper calculated 7 radix places of inary number. A simulation data for the verification is based on the data of algorithm simulation. When the same input data is applied to the both simulation, output results of circuit simulation had slight difference in compare with that of algorithm simulation. The number of used gate is about 5,500 and We have 5.53MHz in maximum frequency.y.

• Current Optics and Photonics
• /
• v.1 no.2
• /
• pp.90-94
• /
• 2017

Visible light identification (VLID) is a user identification system for a door lock application using smartphone that adopts visible light communication (VLC) technology with the objective of high security, small form factor, and cost effectiveness. The user is verified by the identification application program of a smartphone via fingerprint recognition or password entry. If the authentication succeeds, the corresponding encoded visible light signals are transmitted by a light emitting diode (LED) camera flash. Then, only a small size and low cost photodiode as an outdoor interface converts the light signal to the digital data along with a comparator, and runs the authentication process, and releases the lock. VLID can utilize powerful state-of-the-art hardware and software of smartphones. Furthermore, the door lock system is allowed to be easily upgraded with advanced technologies without its modification and replacement. It can be upgraded by just update the software of smartphone application or replacing the smartphone with the latest one. Additionally, wireless connection between a smartphone and a smart home hub is established automatically via Bluetooth for updating the password and controlling the home devices. In this paper, we demonstrate a prototype VLID door lock system that is built up with LEGO blocks, a photodiode, a comparator circuit, Bluetooth module, and FPGA board.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.48 no.5
• /
• pp.636-642
• /
• 1999

The synthesis of the 3D images is the most important part of the virtual reality. The ray tracing is the best method for reality in the 3D graphics. But the ray tracing requires long computation time for the synthesis of the 3D images. So, we implement the ray tracing with software and hardware. Specially we design the hit-test unit with FPGA tool for the ray tracing. Hit-test unit is a very important part of ray tracing to improve the speed. In this paper, we proposed a new hit-test algorithm and apply the parallel architecture for hit-test unit to improve the speed. We optimized the arithmetic unit because the critical path of hit-test unit is in the multiplication part. We used the booth algorithm and the baugh-wooley algorithm to reduce the partial product and adapted the CSA and CLA to improve the efficiency of the partial product addition. Our new Ray tracing processor can produce the image about 512ms/F and can be adapted to real-time application with only 10 parallel processors.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.11
• /
• pp.1655-1662
• /
• 1993

In this paper we discuss three algorithms-Direct, Successive, and Recursive-on parallel CRC(Cyclic Redundancy Check) verification. The algorithms are derived by combining the byte-syndromes precomputed from the generator polynomial. These algorithms are compared in terms of the amount of hardware and the speed of operation. Since the algorithms can be generalized easily, we took the ATM cell delineation example for easier description. As an application of the algorithm Recursive, an ATM cell delineation module suitable for STM-1 transmission has been successfully realized through commercially available field programmable gate arrays.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.507-511
• /
• 2010

Digital Radio Frequency Memory (below, DRFM) performs RF signal data store, delay and re-transmission. DRFM is wildly used as core module of Jammer, EW simulator, Target Echo Generator etc. This paper suggests a hardware design of DRFM which is composed RF section(RF Input/Output Module, Local Oscillator Module) and Digital section(ADC module, memory, DAC module), and confirm the validity of the propose by the test result.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.64 no.10
• /
• pp.1460-1468
• /
• 2015

As the number of IoT service increases, the interest of lightweight block cipher algorithm, which consists of simple operations with low-power and high speed, is growing. LEA(Leightweight Encryption Algorithm) is recently adopted as one of lightweight encryption standards in Korea. In this paper a pipeline LEA architecture is proposed to process large amounts of data with high throughput. The proposed pipeline LEA can communicate with external modules in the 32-bit I/O interface. It consists of input, output and encryption pipeline stages which take 4 cycles using a muti-cycle pipeline technique. The experimental results showed that the proposed pipeline LEA achieved more than 7.5 Gbps even though the key length was varied. Compared with the previous high speed LEA in accordance with key length of 128, 192, and 256 bits, the throughput of the pipeline LEA was improved 6.45, 7.52, and 8.6 times. Also the throughput per area was improved 2, 1.82, and 2.1 times better than the previous one.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.8 no.9
• /
• pp.3266-3285
• /
• 2014

With limited computing and storage resources, many network applications of encryption algorithms require low power devices and fast computing components. CHESS-64 is designed by employing simple key scheduling and Data-Dependent operations (DDO) as main cryptographic components. Hardware performance for Field Programmable Gate Arrays (FPGA) and for Application Specific Integrated Circuits (ASIC) proves that CHESS-64 is a very flexible and powerful new cipher. In this paper, the security of CHESS-64 block cipher under related-key differential cryptanalysis is studied. Based on the differential properties of DDOs, we construct two types of related-key differential characteristics with one-bit difference in the master key. To recover 74 bits key, two key recovery algorithms are proposed based on the two types of related-key differential characteristics, and the corresponding data complexity is about $2^{42.9}$ chosen-plaintexts, computing complexity is about $2^{42.9}$ CHESS-64 encryptions, storage complexity is about $2^{26.6}$ bits of storage resources. To break the cipher, an exhaustive attack is implemented to recover the rest 54 bits key. These works demonstrate an effective and general way to attack DDO-based ciphers.

• Journal of the Institute of Convergence Signal Processing
• /
• v.12 no.2
• /
• pp.139-144
• /
• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.