• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.05a
• /
• pp.407-409
• /
• 2015

In this paper, a hardware implementation of MOD(Moving Object Detection) algorithm is described, which is based GMM(Gaussian Mixture Model) and background subtraction. The EGML(Effective Gaussian Mixture Learning) is used to model and update background. Some approximations of EGML calculations are applied to reduce hardware complexity, and pipelining technique is used to improve operating speed. Gaussian parameters are adjustable according to various environment conditions to achieve better MOD performance. MOD processor is verified by using FPGA-in-the-loop verification, and it can operate with 109 MHz clock frequency on XC5VSX95T FPGA device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.719-721
• /
• 2013

A thinning stage of fingerprint algorithm occupies 39% cycle of microprocessor system for identification processing of image from fingerprint sensor. Hardware block processing is more effective than software one in speed and power consumption, because a thinning algorithm is iteration of simple instructions without a transcendental function. This paper describes an effective hardware scheme for thinning stage processing using Verilog-HDL in $64{\times}64$ Pixel Array. The hardware scheme is designed and simulated in RTL. The logic is also synthesized by XST in FPGA environment and tested. Experimental results show the performance of the proposed scheme and possibility of application for a soft microprocessor and thinning processor embedded fingerprint SoC.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.5
• /
• pp.1089-1094
• /
• 2013

In this study, we propose how th implement a MDDI(Mobile Display Digital Interface) protocol packet generation method in software. MDDI protocol is widely used in mobile display device. MDDI protocol packets are generated by software within micro processor. This method needs the minimum hardware configuration. In order to implementation of this method, we design a hardware platform with a high performance microprocessor and a FPGA. The packets generated by software within microprocessor are converted into LVDS signals, and transmitted by hardware within FPGA. This study suggests the benefits of the way how software can easily create a variety of packet. But, this proposed method takes more time in packet transmission compared to the traditional method. This weakness remains as a future challenge, which can be soon improved.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.28 no.5
• /
• pp.1225-1231
• /
• 2018

FPGA-based system development is being developed as a form of outsourcing that shortens the development time and reduces the cost. Through the process, the risk of letting the hardware Trojan, which causes malfunctions, seep into the system also increases. Various detection methods are proposed for the issue; however, such type of hardware Trojans is inserted by modifying a bitstream directly and therefore, it is hard to detect with the suggested methods. To detect the type of hardware Trojans, it is essential to reverse-engineer the electric circuit implemented by bitstream to a distinguishable level. Specifically, it is important to reverse-engineer the routing information of the circuit that can identify the input-output flow of the signal. In this paper, we analyze the BIL bitstream reverse-engineering tool-chain that uses the algorithm, which retrieves the routing information from FPGA bitstream, and suggest the method to improve the tool-chain.

• Journal of Communications and Networks
• /
• v.1 no.3
• /
• pp.201-212
• /
• 1999

This paper studies the rapid design and implementation of the medium access control(MAC) and related interface circuits for 802.11 wireless LANs based on the field programmed gate ar-ray(FPGA) technology. Our design is thus aimed to support both the distributed coordination function (DCF) and the point coordination function(PCF) with the aid of FPGA technology. Further-more, in an infrastructure network, some stations may serve as the access points (APs) which may function like a learning bridge. This paper will also discuss how to design for such application. The hardware of the MAC and interface may at least consist of three major parts: wireless transmission and reception processes and in-terface, host(bus) interface, and the interface to the distributed system (optional). Through the increasing popularity of FPGA de-sign, this paper presents how Complex Programmable Logic De-vices(CPLD) can be utilized for speedy design of prototypes. It also demonstrates that there is much room for low-cost hardware prototype design to accelerate the processing speed of the MAC control function and for field testing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.10a
• /
• pp.363-366
• /
• 2007

This paper evaluated the performance of circuit for compensate the frequency offset in OFDM using Simulink and designed a System Generator model for FPGA implementation. System Generator Model generated HDL code and RTL schematic. Also, evaluate the performance through Hardware Co-simulation, and investigated the result of timing analysis and resource estimation.

• Journal of Power Electronics
• /
• v.12 no.6
• /
• pp.974-981
• /
• 2012

A FPGA based delta modulated single phase matrix converter has been developed that may be used in both cyclo-converters and cyclo-inverters. This converter is ideal for variable speed electrical drives, induction heating, fluorescent lighting, ballasts and high frequency power supplies. The peripheral input-output and FPGA interfacing have been developed through Xilinx 9.2i, to generate delta modulated trigger pulses for the converter. The controller has been relieved of the time consuming computational task of PWM signal generation by implementing the method of trigger pulse generation in a FPGA by using Hardware Description Language VHDL in Xilinx. The trigger circuit has been tested qualitatively by observing various waveforms on an oscilloscope. The operation of the proposed system has been found to be satisfactory.

• The KIPS Transactions:PartC
• /
• v.8C no.1
• /
• pp.32-40
• /
• 2001

In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.3C
• /
• pp.297-305
• /
• 2007

In the paper, a Motion JPEG2000 coder which has been set as the standard for image compression by the Digital Cinema Initiatives (DCI), an organization composed of major movie studios was implemented into a target FPGA. The DWT (Discrete Wavelet Transform) based on lifting and the Tier 1 of EBCOT (Embedded Block Coding with Optimized Truncation) which are major functional modules of the JPEG2000 were setup with dedicated hardware. The Tier 2 process was implemented in software. For digital cinema the tile-size was set to support $1024\times1024$ pixels. To ensure the real-time operations, three entropy encoders were used. When Verilog-HDL was used for hardware, resources of 32,470 LEs in Altera's Stratix EP1S80 were used, and the hardware worked stably at the frequency of 150Mhz.

• Journal of the Korea Computer Graphics Society
• /
• v.23 no.3
• /
• pp.55-64
• /
• 2017

In this paper, a novel soft shadow method is suggested to support realistic shadows in mobile ray tracing. In ray tracing, soft shadow is generally generated by sampling a shadow ray. As this sampling method increases the number of rays to be processed, it has undermined the performance. We designed the proposed soft shadow processing method and hardware architecture to overcome this problem through selective shadow generation and triangle address caching for minimizing the performance degradation caused by sampling. The proposed hardware architecture can be integrated into a mobile ray-tracing hardware and was evaluated in terms of its performance on the FPGA. Based on the results, the rendering performance about 4, 8, and 16 samples were improved, respectively, by 40%, 50%, and 56% on average compared to the previous method, and it was found that the real-time soft shadow processing is feasible with the proposed hardware architecture.