• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.66-76
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• 2009

The motion estimation in video encoding system occupies the biggest part. So, we require the motion estimator with efficient structure for real-time operation. And for motion estimator's implementation, it is desired to design hardware module of an exclusive use that perform the encoding process at high speed. This paper proposes motion estimation detection block(MED), 41 SADs(Sum of Absolute Difference) calculation block, minimum SAD calculation and motion vector generation block based on parallel processing. The parallel processing can reduce effectively the amount of the operation. The minimum SAD calculation and MED block uses the pre-computation technique for reducing switching activity of the input signal. It results in high-speed operation. The MED and 41 SADs calculation blocks are composed of adder tree which causes the problem of critical path. So, the structure of adder tree has changed the most commonly used ripple carry adder(RCA) with carry skip adder(CSA). It enables adder tree to operate at high speed. In addition, as we enabled to easily control key variables such as control signal of search range from the outside, the efficiency of hardware structure increased. Simulation and FPGA verification results show that the delay of MED block generating the critical path at the motion estimator is reduced about 19.89% than the conventional strukcture.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.49-55
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• 2021

Recently, a small tracking radar requires the development of a small millimeter wave tracking radar having a high range resolution that can acquire and track a target in various environments and disable the target system with a single blow. Small millimeter wave tracking radar with high range resolution needs to implement a signal processor that can process wide bandwidth signals in real time and meet the requirements of small tracking radar. In this paper, we designed a signal processor that can perform the role and function of a signal processor for a small millimeter wave tracking radar. The signal processor for the small millimeter wave tracking radar requires the real-time processing of input signal of OOOMHz center frequency and OOOMHz bandwidth from 8 channels. In order to satisfy the requirements of the signal processor, the signal processor was designed by applying the high-performance FPGA (Field Programmable Gate Array) and ADC (Analog-to-digital converter) for pre-processing operations, such as DDC (Digital Down Converter) and FFT (Fast Fourier Transform). Finally, the signal processor of the small millimeter wave tracking radar was verified via performance test.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.13-23
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• 2001

This paper implemented into hardware SEED which is the KOREA standard 128-bit block cipher. First, at the respect of hardware implementation, we compared and analyzed SEED with AES finalist algorithms - MARS, RC6, RIJNDAEL, SERPENT, TWOFISH, which are secret key block encryption algorithms. The encryption of SEED is faster than MARS, RC6, TWOFISH, but is as five times slow as RIJNDAEL which is the fastest. We propose a SEED hardware architecture which improves the encryption speed. We divided one round into three parts, J1 function block, J2 function block J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined one round into three parts, J1 function block, J2 function block, J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined it to make it more faster. G-function is implemented more easily by xoring four extended 4 byte SS-boxes. We tested it using ALTERA FPGA with Verilog HDL. If the design is synthesized with 0.5 um Samsung standard cell library, encryption of ECB and decryption of ECB, CBC, CFB, which can be pipelined would take 50 clock cycles to encrypt 384-bit plaintext, and hence we have 745.6 Mbps assuming 97.1 MHz clock frequency. Encryption of CBC, OFB, CFB and decryption of OFB, which cannot be pipelined have 258.9 Mbps under same condition.

• Journal of Advanced Navigation Technology
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• v.25 no.4
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• pp.305-312
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• 2021

Even though various types of sensors are being used for security applications, radar sensors are being suggested as an alternative due to the privacy issues. Among those radar sensors, PD radar has high-complexity receiver, but, FMCW radar requires fewer resources. However, FMCW has disadvantage from the use of 2D-FFT which increases the complexity, and it is difficult to distinguish people from objects those are stationary. In this paper, we present the design and the implementation results of the radar signal processor (RSP) that can distinguish between people and object by respiration measurement using phase estimation without 2D-FFT. The proposed RSP is designed with Verilog-HDL and is implemented on FPGA device. It was confirmed that the proposed RSP includes 6,425 LUT, 4,243 register, and 12,288 memory bits with 92.1% accuracy for target's breathing status.

• Journal of the Korea Society of Computer and Information
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• v.14 no.11
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• pp.97-103
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• 2009

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2323-2329
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• 2013

Web-services employ an XML to represent data and an XML parser is needed to use data. The DOM(Document Object Model) is widely used to parse an XML, but it is not suitable for any systems with limited resources because it requires a preprocessing to create the DOM and additional memory space. In this paper, we propose the StreXTree(Streaming XML Tree) with failure transitions and without any preprocessing tasks in order to improve the system performance. Compared to other works, our StreXTree parser achieves 2.39x and 3.02x improvement in system performance in Search and RBStreX, respectively. In addition, our StreXTree parser supports Well-Formed checking to verify the syntax and structure of XML.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.73-84
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• 2004

This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.

• Journal of IKEEE
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• v.13 no.4
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• pp.110-115
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• 2009

The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation. The quarter-pixel interpolation is achieved using 6-tap horizontal or vertical FIR filters for luminance data and bilinear FIR filters for chroma data. We propose the architecture for interpolation of luminance and chroma data in H.264 decoders. It is composed of dual-channel pipelined processing elements and can interpolate integer-, half- and quarter-pixel data. The number of the processing cycles is different depending on the position. The processing elements are composed of adders and shifters to reduce the complexity while the accuracy of the pixel data are maintained. We design interpolators for luminance and chroma data using Verilog-HDL and verify the function and performance by implementing using an FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.11
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• pp.2169-2177
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• 2015

This paper proposes a new pattern matching module to overcome the increased runtime of previous algorithm using RAM, which was designed to overcome cost limitation of hash-based algorithm using CAM (Content Addressable Memory). By adopting Merge FSM algorithm to reduce the number of state, the proposed module contains state block and entry block to use in RAM. In the proposed module, one input string is compared with multiple entry strings simultaneously using entry block. The effectiveness of the proposed pattern matching unit is verified by executing Snort 2.9 rule set. Experimental results show that the number of memory reads has decreased by 15.8%, throughput has increased by 47.1%, while memory usage has increased by 2.6%, when compared to previous methods.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.1
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• pp.56-62
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• 2011

A Satellite transponder is mounted on the Satellite and performs radio communications with the ground station. A Digital transponder compared to The analog transponder is made easy and accurate performance prediction. Also Modulation Scheme, Data Rate, Loop Bandwidth, Modulation Index and etc. can be changed on orbit, by implementing FPGA can reduce the weight and volume. The core technology of digital transponder is Carrier Recovery loop. Dynamic Range, Frequency Tracking Range, Frequency Tracking Rate and Coherent performance are determined by the performance of the Carrier Recovery loop. In this paper, we proposed the structure of Carrier Recovery loop for the Satellite digital transponder, then tested and verified the structure.