• Proceedings of the KIEE Conference
• /
• 2007.04a
• /
• pp.267-269
• /
• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.5 no.12
• /
• pp.2326-2339
• /
• 2011

To reduce the implementation complexity of the Vertical Bell Labs layered space-time (V-BLAST) systems with respect to the zero-forcing (ZF) criterion, a computationally efficient recursive algorithm is proposed. A fast implementation of the proposed algorithm is developed and its complexity is analyzed in detail. The proposed algorithm matches the ZF-OSIC detection well, and its three significant advantages can be demonstrated by analyses and simulations. Firstly, its speedups over the conventional ZF-OSIC with norm-based ordering, the original fast recursive algorithm (FRA) and the fastest known algorithm (FKA) in the number of flops are 1.58, 2.33 and 1.22, respectively. Secondly, a much simpler implementation than FRA and FKA can be expected. Finally, the storage requirements are lower than those of FRA and FKA. These advantages make the proposed algorithm more efficient and practical.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.5 no.3
• /
• pp.494-507
• /
• 2011

In this paper, we propose two schemes to reduce the complexity of fixed-complexity sphere decoder (FSD) algorithm in the ordering and tree-search stages, respectively, while achieving quasi-ML performance. In the ordering stage, we propose a QR-decomposition-based FSD signal ordering based on the zero-forcing criterion (FSD-ZF-SQRD) that requires only a few number of additional complex flops compared to the unsorted QRD. Also, the proposed ordering algorithm is extended using the minimum mean square error (MMSE) criterion to achieve better performance. In the tree-search stage, we introduce a threshold-based complexity reduction approach for the FSD depending on the reliability of the signal with the largest noise amplification. Numerical results show that in 8 ${\times}$ 8 MIMO system, the proposed FSD-ZF-SQRD and FSD-MMSE-SQRD only require 19.5% and 26.3% of the computational efforts required by Hassibi's scheme, respectively. Moreover, a third threshold vector is outlined which can be used for high order modulation schemes. In 4 ${\times}$ 4 MIMO system using 16-QAM and 64-QAM, simulation results show that when the proposed threshold-based approach is employed, FSD requires only 62.86% and 53.67% of its full complexity, respectively.

• Nuclear Engineering and Technology
• /
• v.48 no.5
• /
• pp.1192-1205
• /
• 2016

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the "IEEE 1164 standard," registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

• Maxillofacial Plastic and Reconstructive Surgery
• /
• v.19 no.3
• /
• pp.243-249
• /
• 1997

The purpose of this study is to describe the clinical availability of a variety of intraoral local flaps in reconstruction of oral soft tissue defects, Forty patients with oral soft tissue defects were treated by tongue, buccinator, palatal, labial, facial artery musculomucosal, buccal fat pad, and masseter muscle crossover flap. Total 43 intraoral flaps were used to reconstruct a variety of intraoral soft tissue defects, such as oronasal fistula, oroantral fistula, traumatic deformities and other. The age of patients ranged from 7 to 72 years, with mean age of 39.6 years. Follow up period ranged from 2 to 66 months, mean follow up period of 21.6 months. There were 9 complications, of which four were partial necrosis, three infections, one total necrosis, and 1 speech problem. Except for total necrosis, most of the recipient sited healed uneventually without severe morbidity. We consider that a variety of intraoral local flaps can be available for reconstruction of small of moderate large intraoral soft tissue defects.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.3
• /
• pp.425-432
• /
• 1995

In this paper we propose a design and implementation technique of a universal automatic test pattern generator(UATPG) which is well suited for VLSI digital circuits. UATPG is designed to extend the capabilities of the existing APTG and to provide a convenient environment to computer-aided design(CAD) users. We employ heuristic techniques in line justification and fault propagation for functional gates during test pattern generation for a target fault. In addition, the flip-flops associated with design for testability (DFT) are exploited for pseudo PIs and pseudo POs to enhance the testabilities of VLSI circuits. As a result, UATPG shows a good enhancement in convenient usage and performance.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
• /
• 2003.10a
• /
• pp.127-130
• /
• 2003

An RSFQ (Rapid Single Flux Quantum) counter can be used as a frequency divider that was an essential part of a programmable voltage standard chip. The voltage standard chip is composed of two circuit parts, a counter and an antenna Analog signal of tens to hundreds ㎓ may be applied to a finline antenna part. This analog signal can be converted to the stream of SFQ voltage pulses by a DC/SFQ circuit. The number of voltage pulses can be reduced by 2n times when they pass through a counter that is composed of n T Flip-Flops (Toggle Flip-Flop). Such a counter can be used not only as a frequency divider, but also to build a programmable voltage standard chip. So, its application range can be telecommunication, high speed RAM, microprocessor, etc. In this work, we have used Xic, WRspice, and L-meter to design an RSFQ counter. After circuit optimization, we could obtain the bias current margins of the T Flip-Flop circuit to be above 31％ Our RSFQ counter circuit designs were based on the 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.1C
• /
• pp.140-148
• /
• 2008

Using the self duality of an optimal normal basis(ONB) of type II, we present a bit parallel and bit serial systolic arrays over GF($2^m$) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches(flip-flops). Comparing with other arrays of the same kinds, we find that our array has significantly reduced latency and hardware complexity.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2001.10a
• /
• pp.313-316
• /
• 2001

At the end of 1999, the TeraCluster project in the KISTI Supercomputing Center was initiated to explore the possibility of PC clusters as a scientific computing platform to replace the Cray T3E system in KISTI by the year 2002. In order to understand whether an application is scalable to tera-flops sized cluster system, running test is inevitable. Extensive performance tests using well-known benchmarking codes with real applications' characteristics in them were carried out with different combinations of CPUs, system boards, network devices. The lessen learned shows the relationships between system performances and varied applications' different needs resulting in promises of How-Tos in building large scale cluster system. The 64/16 node clusters with Alpha EV6(466MHz), Pentium III(667 MHz) i inter-node network of Fast Ethernet. SCI[1] and Myrinet[2] were evaluated. More detailed specifications of the Linux clusters are described in Table 1.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.5 no.2
• /
• pp.330-343
• /
• 2011

In this paper, we propose two schemes to reduce the complexity of fixed-complexity sphere decoder (FSD) algorithm in the ordering and tree-search stages, respectively, while achieving quasi-ML performance. In the ordering stage, we propose a QR-decomposition-based FSD signal ordering based on the zero-forcing criterion (FSD-ZF-SQRD) that requires only a few number of additional complex flops compared to the unsorted QRD. Also, the proposed ordering algorithm is extended using the minimum mean square error (MMSE) criterion to achieve better performance. In the tree-search stage, we introduce a threshold-based complexity reduction approach for the FSD depending on the reliability of the signal with the largest noise amplification. Numerical results show that in $8{\times}8$ MIMO system, the proposed FSD-ZF-SQRD and FSD-MMSE-SQRD only require 19.5% and 26.3% of the computational efforts required by Hassibi’s scheme, respectively. Moreover, a third threshold vector is outlined which can be used for high order modulation schemes. In $4{\times}4$ MIMO system using 16-QAM and 64-QAM, simulation results show that when the proposed threshold-based approach is employed, FSD requires only 62.86% and 53.67% of its full complexity, respectively.