• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.1
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• pp.31-40
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• 2023

Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.

• Journal of IKEEE
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• v.25 no.4
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• pp.778-781
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• 2021

In this paper, we propose the 16-layer 3D NAND Flash memory compact modeling using SPICE. In the same structure and simulation conditions, the channel potential about Down Coupling Phenomenon(DCP) and Natural Local Self Boosting (NLSB) were simulated and analyzed with Technology Computer Aided Design(TCAD) tool Atlas(Silvaco^TM) and SPICE, respectively. As a result, it was confirmed that the channel potential of TCAD and SPICE for the two phenomena were almost same. The SPICE can be checked the device structure intuitively by using netlist. Also, its simulation time is shorter than TCAD. Therefore, using SPICE can be expected to efficient research on 3D NAND Flash memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.537-542
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• 2014

The three-dimensional (3-D) NAND flash structure with fully charge storage using edge fringing field effect is presented, and its programming characteristic is evaluated. We successfully confirmed that this structure using fringing field effect provides good program characteristics showing sufficient threshold voltage ($V_T$) margin by technology computer-aided design (TCAD) simulation. From the simulation results, we expect that program speed characteristics of proposed structure have competitive compared to other 3D NAND flash structure. Moreover, it is estimated that this structural feature using edge fringing field effect gives better design scalability compared to the conventional 3D NAND flash structures by scaling of the hole size for the vertical channel. As a result, the proposed structure is one of the candidates of Terabit 3D vertical NAND flash cell with lower bit cost and design scalability.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• Journal of the Korea Society of Computer and Information
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• v.26 no.11
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• pp.1-9
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• 2021

3D-NAND flash memory provides high capacity per unit area by stacking 2D-NAND cells having a planar structure. However, due to the nature of the lamination process, there is a problem that the frequency of error occurrence may vary depending on each layer or physical cell location. This phenomenon becomes more pronounced as the number of write/erase(P/E) operations of the flash memory increases. Most flash-based storage devices such as SSDs use ECC for error correction. Since this method provides a fixed strength of data protection for all flash memory pages, it has limitations in 3D NAND flash memory, where the error rate varies depending on the physical location. Therefore, in this paper, pages and layers with different error rates are classified into clusters through the K-means machine learning algorithm, and differentiated data protection strength is applied to each cluster. We classify pages and layers based on the number of errors measured after endurance test, where the error rate varies significantly for each page and layer, and add parity data to stripes for areas vulnerable to errors to provides differentiate data protection strength. We show the possibility that this differentiated data protection policy can contribute to the improvement of reliability and lifespan of 3D NAND flash memory compared to the protection techniques using RAID-like or ECC alone.

• Journal of IKEEE
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• v.25 no.4
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• pp.770-773
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• 2021

In this paper, the retention characteristics of 3D NAND flash memory applied with tapering and ferroelectric (HfO₂) structure were analyzed after programming operation. Electrons trapped in nitride are affected by lateral charge migration over time. It was confirmed that more lateral charge migration occurred in the channel thickened by tapering of the trapped electrons. In addition, the Oxide-Nitride-Ferroelectric (ONF) structure has better lateral charge migration due to polarization, so the change in threshold voltage (V_th) is reduced compared to the Oxide-Nitride-Oxide (ONO) structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.566-571
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• 2014

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

• Journal of Korea Game Society
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• v.9 no.1
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• pp.85-91
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• 2009

In the recent development of 3D game, the importance of the game interface as well as the amusement and performance of the game is highlighted. Considering the fact that the flash can easily express the various multimedia contents will provide new possibilities and improve the presentation of game interfaces, the system using the flash in 3D PC game interface was designed and tested in this paper.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2007.11a
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• pp.909-914
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• 2007

Today's dynamic nature of the construction environment requires management systems to be active enough to take real-time decisions. For real-time decision making, effective 3D spatial information acquisition is imperative. Various 3D data acquisition technologies are being developed and tested for 3D spatial information acquisition and its use for wide range of areas in the construction industry, however, there are shortcomings in these technologies. The major problems are long processing time and high cost which make current technologies impossible to be used for real-time applications. Laser-based Flash LADAR that illuminates the entire scene with diffuse laser light is comparatively fast and cost effective, therefore it is well suited for 3D spatial modeling of dynamic environment on a construction site. This paper presents experimental results to evaluate the performance of flash LADAR and discuss issues of applicability of Flash LADAR to 3D spatial modeling on a construction site.

• Journal of IKEEE
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• v.25 no.4
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.