• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1682-1691
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• 2015

In this paper, a real time implementation of selective harmonic elimination pulse width modulation (SHEPWM) using Real Coded Genetic Algorithm (RGA), Particle Swarm Optimization technique (PSO) and a new technique known as Linearization Method (LM) for Single Phase Matrix Converter (SPMC) is designed and discussed. In the proposed technique, the switching frequency is fixed and the optimum switching angles are obtained using simple mathematical calculations. A MATLAB simulation was carried out, and FFT analysis of the simulated output voltage waveform confirms the effectiveness of the proposed method. An experimental setup was also developed, and the switching angles and firing pulses are generated using Field Programmable Gate Array (FPGA) processor. The proposed method proves that it is much applicable in the industrial applications by virtue of its suitability in real time applications.

• ETRI Journal
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• 제24권5호
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• pp.391-397
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• 2002

This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high-speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 ${\mu}m$ standard cell library, and then verified the functions thoroughly.

• 전자공학회논문지B
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• 제32B권7호
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• pp.1025-1035
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• 1995

In this paper, we realize a real time digital FM synthesizer based on genetic algorithm using a general purpose digital signal processor. Especially, we synthesize diverse music sounds nicely using a synthesis model consisting of a single modulator and multiple carriers. Also we present genetic algorithm-based technique which determines optimal parameters for reconstruction through FM synthesis of a sound after analyzing the spectrum of PCM data as a standard music sound using FFT. Using the suggested parameter extractiuon algorithm, we extract parameters of several instruments and then synthesize digital FM sounds. To verify the validity of the parameter extraction algorithm as well as realization of a real time digital music synthesizer, the evaluation is first done by listening the sound directly as subjective test. Secondly, to evaluate the synthesized sound objectively with an engineering sense, we compare the synthesized sound with an original one in a time domain and a frequency domain.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.229-234
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• 2007

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.97-97
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• 2000

In this paper, a signal processing algorithm for software GPS receiver is proposed. The signal processor takes snapshot of the sampled If signal from the RF section of the GPS receiver. All the processing for code and carrier tracking and correlation are implemented using the digital signal processing techniques. In order to achieve fast code acquisition, correlation of the incoming GPS signal is performed using the FFT method, After code acquisition, to reduce the Doppler shift effect and increase the accuracy, the interpolation or the tracking are performed. The performance of the proposed processing algorithm is first evaluated using matlab/simulink. A signal acquisition board for sampling and logging GPS IF signal form the Mitel GPS RF chip set is constructed. In order to analyze the performance of the designed algorithm the experiments are performed and the results are analyzed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2628-2630
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• 2002

This paper describes the design and implementation of the OFDM Modem using FPGA. The proposed OFDM method is based on IEEE 802.11a high-speed wireless LAN standard. The proposed and designed Pipeline FFT processor adopt the Radix-$2^2$SDF scheme. This method has a simple architecture and highly increases the calculation speed. And also it decreases the required number of registers. Therefore the proposed OFDM Modem reduces hardware size and improves the calculation speed. The OFDM Modem is implemented using $FLEX^{TM}$ FPGA.

• 디지털산업정보학회논문지
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• 제5권4호
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• pp.127-137
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• 2009

This paper is proposed that in-output Digital module is acquired a vibration signal of a rotating machinery by Data Acquisition System. The module is designed to get ride of nose through low pass filter on the vibration signal from sensors and set the gain value for being able to sampling AC to DC, and also the sampled data by sampler and the conversed data by DIP/FPGA is supplied to the analyzer for analysis at a software tool. The DIP(Digital Signal Processor) of the Digital input/output Board makes Average voltage, Peak to Peak voltage, RMS(Root Mean Square) and Gap voltage, also FFT(Fast Fourier Transform) for rotating vibration diagnosis.

• 대한전자공학회논문지
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• 제24권5호
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• pp.777-785
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• 1987

In this paper, a tightly-coupled multiprocessor system is implemented with four processing elements based on MC68000 CPU, a common menory (128KB), and a single time-shared bus. The multi-tasking operating system, MTOS, is modified so that the multiprocessor system can support multitasking and multiprocessing. The performance of the proposed system is evaluated by stochastic Petri Net system modeling. The efficiency and the processing power are simulated for various load factors and up to 16 PEs. By running benchmark programs, such as quicksort, FFT, and matrix-multiplication, the speed of parallel processing is compared with that of a single processor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3153-3155
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• 1999

최근 수년간 의료영상분야는 국내외적으로 급격한 발전을 거듭하고 있다. 특히 자기공명영상장치 (Magnetic Resonance Imaging), X-ray CT(Computed Tomography)와 단층촬영장치는 인체내부를 비침습적(non-invasive)으로 영상화함으로써 해부학적인 질병진단에 많은 장점을 가지고 있다. 이와같은 단층영상 재구성에는 역매트릭스법(matrix inversion). 반복재구성법(interative method), 역투영 법(back-projection), 2차원 Fourier 변환법(2D FFT), 중첩재구성법(Filtered back-projection) 등의 다양한 알고리즘을 사용하고 있다. 본 연구에서는 X-ray CT에서의 단층영상재구성 기법 중 널리 사용되고 있는 Filtered Back Projection 기법의 연산순서도와 연산량을 분석하고 이를 시뮬레이션을 통하여 확인하고 실시간 영상재구성을 위하여 범용 Digital Signal Processor의 병렬처리시스템 구성에 기반된 최적 Architecture를 선정하고자 한다.

• 한국항행학회논문지
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• 제10권2호
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• pp.173-180
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• 2006

비행체 탑재 레이다는 기상에 관계없이 전천후로 비행체의 안전항행, 임무감시, 사격통제, 충돌회피, 이착륙 등 비행에 필수적인 항공장치이다. 본 논문에서는 비행체 탑재 다중 모드 펄스 도플러 레이다 시험 모델의 설계, 제작 및 비행시험 결과를 제시한다. 레이다 시스템은 안테나부, 송수신부, 신호처리부와 전시부의 4-LRU(Line Replacement Unit)로 구성되며, 개발기술은 평판 슬롯 배열 안테나, TWTA 송신기, coherent I/Q detector, 디지털 펄스 압축, 도플러 FFT 필터를 기반으로 한 DSP, 적응 CFAR, TWS 추적 처리기, 비행정보 IMU 및 도플러 추정보상 기법을 포함한다. 개발된 레이다 시스템의 설계 성능은 다양한 헬기탑재 비행시험을 통하여 기능 및 성능을 확인하였다.