• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.498-503
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• 2009

As for Hadamard Transform, because the calculation time of this transform is slower than Discrete Cosine Transform (DCT) and Fast Fourier Transform (FFT), the effectiveness and the practicality are insufficient. Then, the computational complexity can be decreased by using the butterfly operation as well as FFT. We composed calculation time of FFT with that of Fast Complex Hadamard Transform by constructing the algorithm of Fast Complex Hadamard Transform. They are indirect conversions using program of complex number calculation, and immediate calculations. We compared calculation time of them with that of FFT. As a result, the reducing the calculation time of the Complex Hadamard Transform is achieved. As for the computational complexity and calculation time, the result that quadrinomial Fast Complex Hadamard Transform that don't use program of complex number calculation decrease more than FFT was obtained.

• Tribology and Lubricants
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• v.14 no.4
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• pp.121-127
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• 1998

In this study, a numerical procedure to solve a contact problem has been developed. The procedure takes advantage of signal processing technique in frequency domain to achieve shorter computing time. Boussinesq's equation was adopted as the response function. This procedure is applicable to a non-periodic surface profile as well as a periodic one. The validity of this procedure has been established by comparing the numerical results with the exact solutions. The fastness of this procedure was shown in comparison with other algorithm.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.215-222
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• 2005

The efficient utilization of cache memories is a key factor in achieving high performance for computing large signal transforms. Nonunit stride access in computation of large DFTs causes cache conflict misses, thereby resulting in poor cache performance. It leads to a severe degradation in overall performance. In this paper, we propose a dynamic data layout approach considering the memory hierarchy system. In our approach, data reorganization is performed between computation stages to reduce the number of cache misses. Also, we develop an efficient search algorithm to determine the optimal tree with the minimum execution time among possible factorization trees considering the size of DFTs and the data access stride. Our approach is applied to compute the fast Fourier Transform (FFT). Experiments were performed on Pentium 4, $Athlon^{TM}$ 64, Alpha 21264, UtraSPARC III. Experiment results show that our FFT achieve performance improvement of up to 3.37 times better than the previous FFT packages.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.101-108
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• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show $61.02\%$ cell area reduction comparison with those of the conventional multiplier butterfly structure. furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show $46.1\%$ cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.835-838
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• 2000

Popular methods for extracting a text region in video images are in general based on analysis of a whole image such as merge and split method, and comparison of two frames. Thus, they take long computing time due to the use of a whole image. Therefore, this paper suggests the faster method of extracting a text region without processing a whole image. The proposed method uses line sampling methods, FFT and neural networks in order to extract texts in real time. In general, text areas are found in the higher frequency domain, thus, can be characterized using FFT The candidate text areas can be thus found by applying the higher frequency characteristics to neural network. Therefore, the final text area is extracted by verifying the candidate areas. Experimental results show a perfect candidate extraction rate and about 92% text extraction rate. The strength of the proposed algorithm is its simplicity, real-time processing by not processing the entire image, and fast skipping of the images that do not contain a text.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.11
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• pp.1256-1261
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• 2009

Today, implementation of the defect detection in laser welding has been researched for a long time, but most studies have been made around thin plate within $1{\sim}3mm^t$. Therefore, this study was measured and analyzed light emission signals of the induced plasma in $CO_2$ laser lap welding of $6mm^t$ Zn primer-coated steel, and based on this analysis, research made an investigation into possibility of monitoring in thick plate welding. It was been analyzing the measured signals by RMS and FFT processing, as a results, we were able to confirm definite difference of two signals between humping bead and sound bead. Thus, possibility of real time monitoring in $CO_2$ laser lap welding verified experimentally.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.372-381
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• 2014

This study examined a radar signal active cancelation technique, which is a theoretical way of achieving stealth by employing a baseband process that involves sampling the incoming hostile radar signal, analyzing its characteristics, and generating countermeasure signals to cancel out the linear-FM signal of the hostile radar signal reflected from the airborne target. To successfully perform an active cancelation, the effects of errors in the countermeasure signal were first analyzed. To generate the countermeasure signal that requires very fast and accurate processing, the down-sampling technique with the suboptimal maximum likelihood estimation (sMLE) scheme was proposed to improve the speed of the estimation process while preserving the estimation accuracy. The simulation results showed that the proposed down-sampling technique using a 2048 FFT size yields substantial power reduction despite its small FFT size and exhibits similar performance to the sMLE scheme using the 32768 FFT size.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.944-949
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• 1986

By improving the ability of arithmatic processing with an arithmatic processor in a microcomputer and realizing the data input system for real time analysis, an FFT analyzer that is usable within the range of audio frequency is designed and constructed. The input signal passes through a gain programmable pre-amplifier and anti-aliasing lowpass filter into an analogditital converter to be converted into digital form. The converted input data is processed by an Apple II microcomputer. The results of the processing are displayed using a microcomputer display unit and can be copied on a printer or stored in a floppy disk.

• Journal of the Korea Society of Computer and Information
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• v.11 no.4 s.42
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• pp.55-60
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• 2006

The proposed method uses FFT(Fast Fourier Transform) and neural networks in order to extract texts in real time. In general, text areas are found in the higher frequency domain, thus, can be characterized using FFT. The neural network are learned by character region(high frequency) and non character region(low frequency). The candidate text areas can be thus found by applying the higher frequency characteristics to neural network. Therefore, the final text area is extracted by verifying the candidate areas. Experimental results show a perfect candidate extraction rate and about 95% text extraction rate. The strength of the proposed algorithm is its simplicity, real-time processing by not processing the entire image.

• Journal of IKEEE
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• v.24 no.3
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• pp.797-802
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• 2020

In this paper, we presents the design and implementation results of the FFT processor, which supports 4096 points of operation with less memory by sharing several memory used in the base-4 systolic array FFT processor into one memory. Sharing memory provides the advantage of reducing the area, and also simplifies the flow of data as I/O of the data progresses in one memory. The presented FFT processor was implemented and verified on the FPGA device. The implementation resulted in 51,855 CLB LUTs, 29,712 CLB registers, 8 block RAM tiles and 450 DSPs, and confirmed that the memory area could be reduced by 65% compared to the existing base-4 systolic array structure.