• 제어로봇시스템학회논문지
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• 제20권7호
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• pp.706-712
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• 2014

The inverters used to drive Brushless DC motors (BLDC) include switching devices such as FETs and the faults in FETs cause severe performance degradation in systems where a BLDC acts as actuator. This paper presents a fault detection and isolation method for the FETs of an inverter for BLDC motor control systems, which is based on the EKF (Extended Kalman filter). Firstly, an equivalent circuit model for a BLDC motor plus its inverter system was derived. Secondly, a state-space equation was established, where the on-resistance of the FETs is expressed as a state variable and the EKF equation estimates the on-resistance. If the estimated resistance differs greatly from the known value, it can be asserted that there is a fault on that FET. Thirdly, the local convergence of the established EKF was proved. Finally, through the experiments, the performance of the proposed method was verified. The results show that the on-resistance is estimated close to the value specified in the FET data sheet in normal operation, whereas the estimated resistance is a much larger value than the normal one in case an FET fault occurs. Therefore, it is confirmed that the proposed fault detection and isolation method works appropriately in real systems.

• 전자공학회논문지
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• 제52권3호
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• pp.190-195
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• 2015

돌연변이 및 유전병의 원인이 되고 있는 유전자 단일염기 다형성(single nucleotide polymorphisms; SNPs) 검출은 조기진단, 치료 및 제약등 바이오관련 분야에서 매우 중요하다. SNPs 검출을 위한 방법은 다양하게 제시되고 있으나 상보적 DNA와 SNPs의 에너지 차이가 미세하여 SNPs 검출에는 많은 어려움이 존재한다. 본 논문에서는 SNPs를 검출하기 위하여 전하 검출형 전계효과 트랜지스터(field-effect transistors; FETs)를 이용하여 DNA가 가지고 있는 음전하 측정 방법으로 SNPs를 검출하였다. 상보적 DNA와 SNPs의 미세한 에너지 차이를 구분하기 위하여 타게트 DNA hybridization공정에서 드레인-소스 전극에 -0.3 V의 음전압을 인가하였다. 음전압 인가에 따라 DNA 자체 음전하와 센서 표면의 음전압의 전기적 반발력에 의해 센서에 검출되는 타게트 DNA hybridization 신호 크기는 감소하였으나 상보적 DNA와 SNPs의 신호 차는 1.7 mV에서 8.7 mV로 5배 이상 증가하여 검출되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.427-435
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• 2014

Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of $HfO_2$ (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with $HfO_2$, and the VSTI region is filled with $SiO_2$) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with $HfO_2$, and the STI region is filled with $SiO_2$) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate ($C_{gg}$) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest $C_{gg}$ value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.

• Journal of information and communication convergence engineering
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• 제14권1호
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• pp.40-44
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• 2016

The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T_ILD and dielectric constant ε_r of the inter-layer distance (ILD), the doping concentration N_d (N_a), and length L_g of the channel, and the side-wall length L_SW where the stacked FETs are coupled are studied. When N_d (N_a) < 10¹⁶ cm^-3 and L_SW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d (N_a) > 10¹⁶ cm^-3 or L_SW > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or ε_r do not meet the above conditions, the interaction must be taken into consideration.

• 전자공학회논문지
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• 제52권10호
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• pp.64-69
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• 2015

본 연구에서는 실제적 구조를 가지는 bulk와 SOI FinFET에서의 self-heating 효과를 3차원 TCAD 전산모사를 통하여 분석하였다. 기존 연구들에서와 마찬가지로 self-heating 효과에 의해 나타나는 정적인 구동전류의 감소는 SOI FinFET에서 bulk FinFET보다 더 심각함을 보여주고 있다.. 그러나 고속의 logic 동작 및 실제적 구조를 감안하면 SOI FinFET에서의 동적 self-heating 효과는 bulk FinFET과 큰 차이가 없음을 강조한다.

• 센서학회지
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• 제14권5호
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• pp.331-336
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• 2005

The influence of water molecule on the electrical properties of single-walled carbon nanotube field effect transistors (SWNT-FETs) was reported. Conductance suppression was observed with the increase of the humidity. This can be explained by doping of the SWNT-FETs, which has p-type semiconductor characteristic, with the water molecules acting as an electron donor. However, after 65 % of humidity, conductance of the SWNT-FETs started to increase again, due to the opening of electron channels. Upon annealing at $400^{\circ}C$ in Ar atmosphere, conductance increases more than 500 %, and the threshold voltage shifts toward further positive gate voltages. The results of this experiment support possible application of single-walled carbon nanotubes for humidity sensing material.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.27.2-27.2
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• 2011

Polymer electronics is the one of the most promising way to realize the flexible electronics and many studies made remarkable progress to achieve the improvement in performance of polymer electronics comparable to current silicon-based technology. PBTTT is conjugated semiconducting polymer with highly ordered, chain-extended crystalline microstructures and shows high field effect mobilities above 0.1 $cm^2/Vs$. We studied PBTTTs FETs phase and explored methods to control channel interface in various device structures. Especially, in PBTTTs' unique nano-ribbon phase, we could obtain high mobilities of up to 0.4 $cm^2/Vs$, which was not reached before. Alignment of PBTTTs film was carried out using zone casting and anisotropy of mobilities in parallel and perpendicular to the polymer chain direction was investigated. Optical anisotropy in aligned nano-ribbon PBTTT FETs was also studied using a polarized optical absorption.

• Transactions on Electrical and Electronic Materials
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• 제14권3호
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• pp.156-159
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• 2013

The electrical properties of ZnO nanowire field effect transistors (FETs) have been investigated depending on various diameters of nanowires. The ZnO nanowires were synthesized with an Au catalyst on c-plane $Al_2O_3$ substrates using hot-walled pulsed laser deposition (HW-PLD). The nanowire FETs are fabricated by conventional photo-lithography. The diameter of ZnO nanowires is simply controlled by changing the thickness of the Au catalyst metal, which is confirmed by FE-SEM. It has been clearly observed that the ZnO nanowires showed different diameters simply depending on the thickness of the Au catalyst. As the diameter of ZnO nanowires increased, the threshold voltage of ZnO nanowires shifted to the negative direction systematically. The results are attributed to the difference of conductive layer in the nanowires with different diameters of nanowires, which is simply controlled by changing the catalyst thickness. The results show the possibility for the simple method of the fabrication of nanowire logic circuits using enhanced and depleted mode.

• 한국고분자학회:학술대회논문집
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• 한국고분자학회 2006년도 IUPAC International Symposium on Advanced Polymers for Emerging Technologies
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• pp.168-168
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• 2006

Low-operating voltage organic field-effect transistors (OFETs) have been realized with high dielectric constant (${\kappa}$) polymer such as cyanoethylated poly vinyl alcohol (CR-V, ${\kappa}=12$). Since the $high-{\kappa}$polymers are likely to contain water and ionic impurities, large hysteresis and considerable leakage current are frequently observed in OFETs. To solve these problems, we cross-linked the CR-V by using a cross-linking agent. Cross-linked CR-V dielectrics showed high dielectric constant of 11.1 and good insulating properties, resulting in a high capacitance ($81nF/cm^{2}$ at 1MHz) at 120 nm of dielectric thickness. Pentacene FETs with cross-linked CR-V dielectrics exhibited high carrier mobility ($0.72\;cm^{2}/Vs$), small subthreshold swing (185 mV/dec) and little hysteresis at low-operating voltage (${\Leq}-3V$).

• Advances in nano research
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• 제3권1호
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.