• Title/Summary/Keyword: FBD

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MuGenFBD: Automated Mutant Generator for Function Block Diagram Programs (MuGenFBD: 기능 블록 다이어그램 프로그램에 대한 자동 뮤턴트 생성기)

  • Liu, Lingjun;Jee, Eunkyoung;Bae, Doo-Hwan
    • KIPS Transactions on Software and Data Engineering
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    • v.10 no.4
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    • pp.115-124
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    • 2021
  • Since function block diagram (FBD) programs are widely used to implement safety-critical systems, effective testing for FBD programs has become important. Mutation testing, a fault-based testing, is highly effective in fault detection but computationally expensive. To support testers for FBD programs, we propose an automated mutant generator for FBD programs. We designed the MuGenFBD tool with the cost and equivalent mutant issues in consideration. We conducted experiments on real industrial examples to present the performance of MuGenFBD. The results show that MuGenFBD can generate mutants for FBD programs automatically with low probability of equivalent mutants and low cost. This tool can effectively support mutation analysis and mutation-adequate test generation for FBD programs.

Definition of Mutation Operators for FBD Models (FBD 모델 대상 뮤테이션 연산자 정의)

  • Shin, Dong-Hwan;Jee, Eun-Kyoung;Bae, Doo-Hwan
    • Proceedings of the Korean Information Science Society Conference
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    • 2012.06b
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    • pp.184-186
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    • 2012
  • Function Block Diagram (FBD)는 산업용 컴퓨터인 Programmable Logic Controller (PLC)의 표준 프로그래밍 언어 중 하나이다. 다양한 시험 기법들의 오류 검출 효과성을 평가하기 위해 뮤테이션 분석 기법이 널리 쓰이고 있는데, FBD 모델 대상 뮤테이션 분석 기법에 대한 연구는 이루어지지 못하였다. 본 연구에서는 FBD 모델 대상 뮤테이션 분석 기법의 토대가 되는 FBD 모델 뮤테이션 연산자를 제안한다. 이를 위해서 FBD 모델의 특성, 다양한 FBD 모델링 오류, 기존의 뮤테이션 분석 기법에 관한 연구를 포괄적으로 분석하여 FBD 모델에 적합한 뮤테이션 연산자를 정의한다. 실제 산업계에서 쓰이는 FBD 모델을 대상으로 뮤테이션 연산자를 적용하고 평가한다.

A CASE Tool for Automatic Generation of FBD Program from NuSCR Formal Specification (NuSCR 정형 요구사항 명세로부터 FBD 프로그램 자동생성을 위한 CASE 도구)

  • Back, Hyoung-Bu;Yoo, Jun-Beom;Cha, Sung-Deok
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.4
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    • pp.265-269
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    • 2009
  • Formal specification plays important roles in guaranteeing software safety of safety-critical systems such as nuclear power plant's digital control systems. We had developed a technique [1] which synthesizes Function Block Diagram(FBD) programs from NuSCR formal requirements specifications, but it did not be used widely as it had no automatic tool support. FBD is one of the programming languages for Programmable Logic Controllers(PLC) based system. This paper introduces a CASE tool, NuSCRtoFBD, developed to automate the synthesis procedure. The CASE tool NuSCRtoFBD can reduce a number of errors occurred in the process of manual FBD programming.

A Formal Verification Technique for PLC Programs Implemented with Function Block Diagrams (함수 블록 다이어그램으로 구현된 PLC 프로그램에 대한 정형 검증 기법)

  • Jee, Eun-Kyoung;Jeon, Seung-Jae;Cha, Sung-Deok
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.3
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    • pp.211-215
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    • 2009
  • As Programmable Logic Controllers (PLCs) are increasingly used to implement safety critical systems such as nuclear instrumentation & control system, formal verification for PLC based programs is becoming essential. This paper proposes a formal verification technique for PLC program implemented with function block diagram (FBD). In order to verify an FBD program, we translate an FBD program into a Verilog model and perform model checking using SMV model checker We developed a tool, FBD Verifier, which translates FBD programs into Verilog models automatically and supports efficient and intuitive visual analysis of a counterexample. With the proposed approach and the tool, we verified large FBD programs implementing reactor protection system of Korea Nuclear Instrumentation and Control System R&D Center (KNICS) successfully.

A Structural Testing Strategy for PLC Programs Specified by Function Block Diagram (함수 블록 다이어그램으로 명세된 PLC 프로그램에 대한 구조적 테스팅 기법)

  • Jee, Eun-Kyoung;Jeon, Seung-Jae;Cha, Sung-Deok
    • Journal of KIISE:Software and Applications
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    • v.35 no.3
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    • pp.149-161
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    • 2008
  • As Programmable Logic Controllers(PLCs) are frequently used to implement real-time safety critical software, testing of PLC software is getting more important. We propose a structural testing technique on Function Block Diagram(FBD) which is one of the PLC programming languages. In order to test FBD networks, we define templates for function blocks including timer function blocks and propose an algorithm based on the templates to transform a unit FBD into a flowgraph. We generate test cases by applying existing testing techniques to the generated flowgraph. While the existing FBD testing technique do not consider infernal structure of FBD to generate test cases and can be applied only to FBD from which the specific intermediate model can be generated, this approach has advantages of systematic test case generation considering infernal structure of FBD and applicability to any FBD without regard to its intermediate format. Especially, the proposed method enables FBD networks including timer function blocks to be tested thoroughly. To demonstrate the effectiveness of the proposed method, we use trip logic of bistable processor of digital nuclear power plant protection systems which is being developed in Korea.

Microprocessor FBD Visualization (마이크로프로세서 FBD 시각화)

  • 이정원;이기호
    • Proceedings of the Korean Information Science Society Conference
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    • 1999.10c
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    • pp.36-38
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    • 1999
  • 하드웨어의 제품 사양에는 제품의 특징, FBD(Functional Block Diagram), 핀의 기능 및 배열, 프로그래밍 모드 및 각 블록의 기능 등이 함께 제시된다. 이 때 다른 사양과는 달리 설계 초기 단계부터 설정되는 가장 개념적인 FBD는 마이크로프로세서의 경우 메모리 인터페이스, 레지스터 파일, 데이터패스, 예외처리기, 각종 제어기, 타이머 등으로 구성된다. FBD의 각 블록들은 여러 명의 설계자들에게 분할되고 이 중 마이크로프로세서 설계의 대부분의 시간을 소비하게 되는 각종 제어기의 설계는 여러 블록이 공동으로 제어 신호를 공유하게 된다. 이 신호에 의해 전체 시스템의 정확성(correctness)이 결정되므로 제어기예서 각 블록에 공급하는 제어 신호는 적절할 타이밍에 정확한 값을 가져야만 한다. 따라서 본 논문은 마이크로프로세서에서의 각 블록에 공급하는 제어 신호는 적절한 타이밍에 정확한 값을 가져야만 한다. 따라서 본 논문은 마이크로프로세서의 FBD를 모델링할 수 있는 시각도구를 제안함으로써 제어 신호에 따른 전체 블록의 유기적인 데이터 흐름을 한 눈에 파악할 수 있도록 한다. 이는 설계초기부터 각 블록들을 설계하는 설계자들간의 공통의 다이어그램인 FBD를 중심으로 설계를 해나감으로써 대화 오류를 감소시키고 제어신호 디버깅을 용이하게 하여 설계시간을 단축시키는 것을 목표로 한다.

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A Study on 8kbps FBD-MPC Method Considering Low Bit Rate (Low Bit Rate을 고려한 8kbps FBD-MPC 방식에 관한 연구)

  • Lee, See-Woo
    • Journal of Digital Convergence
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    • v.12 no.6
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    • pp.271-276
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    • 2014
  • In a speech coding system using excitation source of voiced and unvoiced, it would be involved a distortion of speech quality in case coexist with a voiced and unvoiced consonants in a frame. In this paper, I propose a method of 8kbps Multi-Pulse Speech Coding(FBD-MPC: Frequency Band Division MPC) by using TSIUVC(Transition Segment Including Unvoiced Consonant) searching, extraction and approximation-synthesis method in a frequency domain. I evaluate the 8kbps MPC and FBD-MPC. As a result, SNRseg of FBD-MPC was improved 0.5dB for female voice and 0.2dB for male voice respectively. Compared to the MPC, SNRseg of FBD-MPC has been improved that I was able to control the distortion of the speech waveform finally. And so, I expect to be able to this method for cellular phone and smart phone using excitation source of low bit rate.

Quantitative measures of thoroughness of FBD simulations for PLC-based digital I&C system

  • Lee, Dong-Ah;Kim, Eui-Sub;Yoo, Junbeom
    • Nuclear Engineering and Technology
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    • v.53 no.1
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    • pp.131-141
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    • 2021
  • Simulation is a widely used functional verification method for FBD programs of PLC-based digital I&C system in nuclear power plants. It is difficult, however, to estimate the thoroughness (i.e., effectiveness or quality) of a simulation in the absence of any clear measure for the estimation. This paper proposes two sets of structural coverage adequacy criteria for the FBD simulation, toggle coverage and modified condition/decision coverage, which can estimate the thoroughness of simulation scenarios for FBD programs, as recommended by international standards for functional safety. We developed two supporting tools to generate numerous simulation scenarios and to measure automatically the coverages of the scenarios. The results of our experiment on five FBD programs demonstrated that the measures and tools can help software engineers estimate the thoroughness and improve the simulation scenarios quantitatively.

Comparative Study on the Epidemiology of Food-Borne Disease Outbreaks in Korea and Japan (한국과 일본의 식중독 발생 역학의 비교연구)

  • Hwang, Sun-Young;Moon, Bo-Youn;Park, Yong-Ho;Lee, Myeong-Jin;Bang, Hyeong-Ae;Rhim, Kook-Hwan;Kim, Jin-Seok;Che, Nong-Hun;Lee, Won-Chang
    • Journal of Food Hygiene and Safety
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    • v.25 no.2
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    • pp.129-132
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    • 2010
  • The epidemiology of reported food-borne disease (FBD) outbreaks from 2001 to 2008 in Korea nd Japan were compared in this study. The outbreak rate of FBD in Japan was significantly higher although the average umber of patient in each outbreak in Korea was much higher. In both countries, summer was the season when most FBD outbreaks occurred. The comparison study revealed that FBD outbreaks in spring were more frequent in Korea, and outbreaks in winter were more frequent in Japan. Almost half of FBD outbreaks were observed at restaurants in both countries while FBD outbreaks at schools and work-places in Korea were much higher than in Japan. The most frequent cause of bacterial FBDs in Korea was pathogenic Escherichia coli followed by Salmonella species. On the other hand, Campylobacter jejuni was the most frequent source of bacterial FBDs in Japan. Norovirus, which is elated to uncontrolled hand hygiene and involvement of ill food workers, was the main cause of viral FBDs in both countries. In conclusion, there are common epidemiological characteristics as well as several differences in FBD outbreaks of Korea and Japan. These are suggested to be originated from the characteristic of climate, food sources, and life styles in two countries. Establishment of stricter control and surveillance system for FBD outbreaks are required or prevention and reduction of FBD outbreaks in both countries.

VERIFICATION OF PLC PROGRAMS WRITTEN IN FBD WITH VIS

  • Yoo, Jun-Beom;Cha, Sung-Deok;Jee, Eun-Kyung
    • Nuclear Engineering and Technology
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    • v.41 no.1
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    • pp.79-90
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    • 2009
  • Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design.