• KIPS Transactions on Software and Data Engineering
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• v.5 no.12
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• pp.615-622
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• 2016

Automotive control software can be a source of critical safety issues when developers do not comply system constraints. However, a violation is difficult to identify in complicated source code if not supported by an automated verification tool. This paper introduces two possible approaches that check whether an automotive control software complies API call constraints to compare their performance and effectiveness. One method statically analyzes the source code and explores all possible execution paths, and the other utilizes a model checker to monitor constraint violations for a given set of constraint automata. We have implemented both approaches and performed a series of experiments showing that the approach with model-checking finds constraint violations more accurately and scales better.

• Journal of the Korea Society for Simulation
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• v.17 no.4
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• pp.153-158
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• 2008

The technology of Software Defined Radio (SDR) is a possible solution to interwork flexibly between various wireless transport protocols. Ubiquitous network, like u-health service network, includes sensor devices or nodes which do not facilitate all the same transport protocols to access network. As such this may be in such unreachable situations as poverty of all required AP (Access Point)’s, faults or contention in a path of particular protocol communication, etc. This paper presents research results of modeling and simulation to analyze transport performance of multi-protocol ubiquitous network which includes SDR-based interwork nodes and congestion-controlled AP’s. Focusing mainly on dynamics of overall transport performance rather than protocol execution procedures, this paper employs the Zeigler’s DEVS (Discrete Event Systems Specification) methodology and DEVSim++simulation environment to experiment.

• Korean Journal of Construction Engineering and Management
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• v.17 no.1
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• pp.83-91
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• 2016

In the past, the domestic construction industry mainly comprised quantitative investment through the supply of labor force, however, there have recently been opinions that there is a need for qualitative investment in the workers in order to obtain competitiveness in construction markets. Accordingly, there are much re-education courses for workers in the construction industry, but there is much negative awareness as to the efficiency of the current re-education course due to many problems. This study aimed to examine the problems o f currently executed re-education courses and proposed an improvement plan for the qualitative enhancement of domestic construction re-education. Thus, a multiple regression analysis was conducted to deduce two core problems an improvement plan. The improvement plan for the problems comprised the NCS/CDP-based integrative education program through an AHP. The contribution of this paper will result in the execution of a more effective construction industry re-education program, and the result of such program to achieve qualitative growth in the workers in the construction industry

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.