• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.61-66
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• 2021

In this study, we studied the alternative of plasma resistant ceramic parts that constitute plasma chambers in the semiconductor dry etching process. MgO-Al₂O₃-SiO₂(MAS) glass was made of 13 types of glass using the Design Of Experiments(DOE) and the effect on thermal properties such as glass transition temperature and crystallization temperature depending on the content of each composition and etching resistance to CF₄/O₂/Ar plasma gas. MAS glass showed excellent plasma resistance and surface roughness up to 20 times higher than quartz glass. As the content of Al₂O₃ and MgO increases, the plasma resistance is improved, and it has been confirmed that it has an inverse relationship with SiO₂.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.72.2-72.2
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• 2010

Nowadays, the crystalline Si Solar cell are expected for economical renewable energy source. The cost of the crystalline Si solar cell are decreasing by improvement of its efficiency and decrease of the cost of the raw Si wafers for Solar cells. This Si wafer based crystalline Si solar cell is the verified technology from several decade of its history. Now, I will introduce one method that can be upgrade the efficiency by using simple and economical method. The name of this method is Rear Side Etching(RSE). The purpose of rear side etching is the elimination of n+ layer of rear side and increase of the flatness. The effects of rear side etching are the improvement of Voc and increase of efficiency by reducement series resistance and forming of uniform BSF. The experimental procedure for rear side etching is very simple. After anti-reflection coating on solar cell wafer, Solar cell wafer is etched by the etching chemical that react with only rear side not front side. This special chemical is no harmful to anti-reflection coating layer. It can only etched rear side of solar cell wafer. We can use etching image by optical microscope, minority carrier life time by WCT 120, SiNx thickness and refractive index by ellipsometer, cell efficiency for the RSE effect measurement. The key point of rear side etching is development of etching process condition that react with only rear side. If we can control this factor, we can achieve increase of solar cell efficiency very economically without new device.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2004년도 춘계학술대회 논문집
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• pp.245-249
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• 2004

Transparent materials such as fused silica are important materials in optical and optoelectronics field because of its outstanding properties, such as transparency in a wide wavelength range, strong damage resistance for laser irradiation, and high thermal and chemical stability. However, these properties make it difficult to micromachine silica in micro-sized quantities. In this study, we fabricated a micro patterns on the surface of fused silica plate using laser induced wet etching. KrF excimer laser was used as a light source. There were no burrs and micro cracks on the etched surface of fused silica and the flatness of the etched surface was fairly good. We investigated the influence of etchant upon the etch rate and quality in laser induced wet etching. Pyrene-acetone, toluene, and pyrene-toluene solution were used as etchant. In the side of etch rate, toluene and pyrene-toluene solution were better than pyrene-acetone solution.

• 반도체디스플레이기술학회지
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• 제21권3호
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• pp.74-79
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• 2022

In this study, the plasma corrosion resistance and the change in the number of contamination particles generated using the plasma etching process and cleaning process of coating parts for semiconductor plasma etching equipment were investigated. As the coating method, atmospheric plasma spray (APS) was used, and the powder materials were Y₂O₃ and Y₃Al₅O₁₂ (YAG). There was a clear difference in the densities of the coatings due to the difference in solubility due to the melting point of the powdered material. As a plasma environment, a mixed gas of CF₄, O₂, and Ar was used, and the etching process was performed at 200 W for 60 min. After the plasma etching process, a fluorinated film was formed on the surface, and it was confirmed that the plasma resistance was lowered and contaminant particles were generated. We performed a surface cleaning process using piranha solution(H₂SO₄(3):H₂O₂(1)) to remove the defect-causing surface fluorinated film. APS-Y₂O₃ and APS-YAG coatings commonly increased the number of defects (pores, cracks) on the coating surface by plasma etching and cleaning processes. As a result, it was confirmed that the generation of contamination particles increased and the breakdown voltage decreased. In particular, in the case of APS-YAG under the same cleaning process conditions, some of the fluorinated film remained and surface defects increased, which accelerated the increase in the number of contamination particles after cleaning. These results suggest that contaminating particles and the breakdown voltage that causes defects in semiconductor devices can be controlled through the optimization of the APS coating process and cleaning process.

• 공업화학
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• 제34권4호
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• pp.444-449
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• 2023

전자 기기의 소형화, 집적화 및 박형화에 따라 인쇄회로기판 제조 시 미세한 회로 패턴이 요구되고 있다. 기존의 인쇄회로기판은 dry film resist를 이용한 photolithography 법을 적용하여 주로 제조하지만, 미세 회로 패턴 구현을 위해서는 정밀한 마스크 설계 및 고가의 노광장비 등이 필요하다는 한계점이 있다. 이에 따라서 최근에는 dry film resist를 대체하여 미세 회로 패턴 형성에 유리한 광경화형 잉크를 직접인쇄 공정을 통해 인쇄회로기판의 회로 패턴을 형성하는 연구들이 관심받고 있다. 광경화형 잉크를 통한 회로 패턴 형성을 위해서는 동박과의 밀착성, 패턴 형성 과정에서의 에칭 저항성, 박리 특성의 제어가 필수적이다. 본 연구에서는 광개시제 종류 및 함량이 다른 여러 광경화형 잉크를 제조하고 이들의 광경화 거동을 분석하였다. 또한, 광경화형 에칭 레지스트 잉크로의 적용성 평가를 위해 에칭 저항성, 박리성, 밀착성 등을 분석하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.244.2-244.2
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• 2013

Contact Pattern을 Plasma Etching을 통해 Pattering 공정을 진행함에 있어서 Plasma 내에 존재하는 High Energy Ion 들의 Bombardment 에 의해, Contact Bottom 의 Silicon Lattice Atom 들은 Physical 한 Damage를 받아 Electron 의 흐름을 방해하게 되어, Resistance를 증가시키게 된다. 또한 Etchant 로 사용되는 Fluorine 과 Chlorine Atom 들은, Contact Bottom 에 Contamination 으로 작용하게 되어, 후속 Contact 공정을 진행하면서 증착되는 Ti 나 Co Layer 와 Si 이 반응하는 것을 방해하여 Ohmic Contact을 형성하기 위한 Silicide Layer를 형성하지 못하도록 만든다. High Aspect Ratio Contact (HARC) Etching 을 진행하면서 Contact Profile을 Vertical 하게 형성하기 위하여 Bias Power를 증가하여 사용하게 되는데, 이로부터 Contact Bottom에서 발생하는 Etchant 로 인한 Damage 는 더욱 더 증가하게 된다. 이 Damage Layer를 추가적인 Secondary Damage 없이 제거하기 위하여 본 연구에서는 원자층 식각방법(Atomic Layer Etching Technique)을 사용하였다. 실험에 사용된 원자층 식각방법을 이용하여, Damage 가 발생한 Si Layer를 Secondary Damage 없이 효과적으로 Control 하여 제거할 수 있음을 확인하였으며, 30 nm Deep Contact Bottom 에서 Damage 가 제거될 수 있음을 확인하였다. XPS 와 Depth SIMS Data를 이용하여 상기 실험 결과를 확인하였으며, SEM Profile 분석을 통하여, Damage 제거 결과 및 Profile 변화 여부를 확인하였으며, 4 Point Prove 결과를 통하여 결과적으로 Resistance 가 개선되는 결과를 얻을 수 있었다.

• 전기전자학회논문지
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• 제13권4호
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• pp.23-27
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• 2009

실리콘 기판 상에 MBE (molecular beam epitaxy)로 형성된 GaSb 기반 p-channel HEMT 소자를 제작하기 위하여 오믹 접촉 형성 공정과 식각 공정을 연구하였다. 먼저 각 소자의 절연을 위한 메사 식각 공정 연구를 수행하였으며, HF기반의 습식 식각 공정과 ICP(inductively coupled plasma)를 이용한 건식 식각 공정이 모두 사용되었다. 이와 함께 소스/드레인 영역 형성을 위한 오믹 접촉 형성 공정에 관한 연구를 진행하였으며 Ge/Au/Ni/Au 금속층 및 $300^{\circ}C$ 60초 RTA공정을 통해 $0.683\;{\Omega}mm$의 접촉 저항을 얻을 수 있었다. 더불어 HEMT 소자의 게이트 형성을 위한 게이트 리세스 공정을 AZ300 현상액과 citric산 기반의 습식 식각을 이용하여 연구하였으며, citric산의 경우 소자 구조에서 캡으로 사용된 GaSb와 베리어로 사용된 AlGaSb사이에서 높은 식각 선택비를 보였다.

• 한국전기전자재료학회논문지
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• 제24권2호
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• pp.152-155
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• 2011

Even though nano-scale materials were very advantageous for various applications, there are still problems to be solved such as the stabilization of surface state and realization of low contact resistances between a semiconducting nanowire and electrodes in nano-electronics. It is well known that the effects of contacts barrier between nano-channel and metal electrodes were dominant in carrier transportation in individual nano-electronics. In this report, it was investigated the electrical properties of GaN nanorod devices after chemical etching and rapid thermal annealing for making good contacts. After KOH wet-etching of the contact area the devices showed better electrical performance compared with non-treated GaN individual devices but still didn't have linear voltage-current characteristics. The shape of voltage-current properties of GaN devices were improved remarkably after rapid thermal annealing as showing Ohmic behaviors with further bigger conductivities. Even though chemical etching of the nanorod surfaces could cause scattering of carriers, in here it was shown that the most important and dominant factor in carrier transport of nano-electronics was realization of low contact barrier between nano-channel and metal electrodes surely.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.279-282
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• 2001

The IBE(ion beam etching)-induced Schottky barrier variation which depends on various etching history related with ion energy, incident angle and etching time has been investigated using voltage-current, capacitance-voltage characteristics of metal-etched silicon contact and morphology of etched surface were studied using AFM(atomic force microscope). For ion beam etched n-type silicons, Schottky barrier is reduced according to ion beam energy. It can be seen that amount of donor-like positive charge created in the damaged layer is proportional to the ion energy. By contrary, for ion beam etched p-type silicons, the Schottky barrier and specific contact resistance are both increased. Not only etching time but also incident angle of ion beam has an effect on barrier height. Taping-mode AFM analysis shows increased roughness RMS(Root-Mean-Square) and depth distribution due to ion bombardment. Annealing in an N$_2$ ambient for 30 min was found to be effective in improving the diode characteristics of the etched samples and minimum annealing temperatures to recover IBE-induced barrier variation were related to ion beam energy.

• 한국재료학회지
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• 제23권6호
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• pp.316-321
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• 2013

The electrical properties and surface morphology changes of a silicon wafer as a function of the HF concentration as the wafer is etched were studied. The HF concentrations were 28, 30, 32, 34, and 36 wt%. The surface morphology changes of the silicon wafer were measured by an SEM ($80^{\circ}$ tilted at ${\times}200$) and the resistivity was measured by assessing the surface resistance using a four-point probe method. The etching rate increased as the HF concentration increased. The maximum etching rate 27.31 ${\mu}m/min$ was achieved at an HF concentration of 36 wt%. A concave wave formed on the wafer after the wet etching process. The size of the wave was largest and the resistivity reached 7.54 $ohm{\cdot}cm$ at an 30 wt% of HF concentration. At an HF concentration of 30 wt%, therefore, a silicon wafer should have good joining strength with a metal backing as well as good electrical properties.