• Membrane Journal
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• v.30 no.1
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• pp.38-45
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• 2020

Although Lithium metal battery (LMB) has a very large theoretical capacity, it has a critical problem such as formation of dendrite which causes short circuit and short cycle life of the LMB. In this study, PDMS/GO composite with evenly dispersed graphene oxide (GO) nanosheets in poly (dimethylsiloxane) (PDMS) was synthesized and coated into a thin film, resulting in the effect that can physically suppress the formation of dendrite. However, PDMS has low ion conductivity, so that we attained improved ion conductivity of PDMS/GO thin film by etching technic using 5wt% hydrofluoric acid (HF), to facilitate the movement of lithium (Li) ions by forming the channel of Li ions. The morphology of the PDMS/GO thin film was observed to confirm using SEM. When the PDMS/GO thin film was utilized to lithium metal battery system, the columbic efficiency was maintained at 87.4% on average until the 100^th cycles. In addition, voltage profiles indicated reduced overpotential in comparison to the electrode without thin film.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.77-77
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• 2000

Titanium oxide (TiO2) thin films have valuable properties such as a high refractive index, excellent transmittance in the visible and near-IR frequency, and high chemical stability. Therefore it is extensively used in anti-reflection coating, sensor, and photocatalysis as electrical and optical applications. Specially, TiO2 have a high dielectric constant of 180 along the c axis and 90 along the a axis, so it is highlighted in fabricating dielectric capacitors in micro electronic devices. A variety of methods have been used to produce patterned self-assembled monolayers (SAMs), including microcontact printing ($\mu$CP), UV-photolithotgraphy, e-beam lithography, scanned-probe based micro-machining, and atom-lithography. Above all, thin film fabrication on $\mu$CP modified surface is a potentially low-cost, high-throughput method, because it does not require expensive photolithographic equipment, and it produce micrometer scale patterns in thin film materials. The patterned SAMs were used as thin resists, to transfer patterns onto thin films either by chemical etching or by selective deposition. In this study, we deposited TiO2 thin films on Si (1000 substrateds using titanium (IV) isopropoxide ([Ti(O(C3H7)4)] ; TIP as a single molecular precursor at deposition temperature in the range of 300-$700^{\circ}C$ without any carrier and bubbler gas. Crack-free, highly oriented TiO2 polycrystalline thin films with anatase phase and stoichimetric ratio of Ti and O were successfully deposited on Si(100) at temperature as low as 50$0^{\circ}C$. XRD and TED data showed that below 50$0^{\circ}C$, the TiO2 thin films were dominantly grown on Si(100) surfaces in the [211] direction, whereas with increasing the deposition temperature to $700^{\circ}C$, the main films growth direction was changed to be [200]. Two distinct growth behaviors were observed from the Arhenius plots. In addition to deposition of THe TiO2 thin films on Si(100) substrates, patterning of TiO2 thin films was also performed at grown temperature in the range of 300-50$0^{\circ}C$ by MOCVD onto the Si(100) substrates of which surface was modified by organic thin film template. The organic thin film of SAm is obtained by the $\mu$CP method. Alpha-step profile and optical microscope images showed that the boundaries between SAMs areas and selectively deposited TiO2 thin film areas are very definite and sharp. Capacitance - Voltage measurements made on TiO2 films gave a dielectric constant of 29, suggesting a possibility of electronic material applications.

• Journal of the Korean Vacuum Society
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• v.15 no.6
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• pp.630-636
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• 2006

Scale down of semiconductor gate pattern will make progress centrally line width into transistor according to the high integration and high density of flash memory semiconductor. Recently, the many researchers are in the process of developing research for using the ONO(oxide-nitride-oxide) technology for the gate pattern give body to line breadth of less 100 nm. Therefore, etch rate and etch profile of the line width detail of less 100 nm affect important factor in a semiconductor process. In case of increasing of the platen power up to 50 W at the ICP etcher, etch rate and PR selectivity showed good result when the platen power of ICP etcher has 100 W. Also, in case of changing of HBr gas flux at the platen power of 100 W, etch rate was decreasing and PR selectivity is increasing. We founded terms that have etch rate 320 nm/min, PR selectivity 3.5:1 and etch slope have vertical in the case of giving the platen power 100 W and HBr gas 35 sccm at the ICP etcher. Also notch was not formed.