• Current Photovoltaic Research
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• v.5 no.3
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• pp.75-82
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• 2017

High efficiency thin film solar cells require an absorber layer with high absorption and low defect, a transparent conductive oxide (TCO) film with high transmittance of over 80% and a high conductivity. Furthermore, light can be captured through the glass substrate and sent to the light absorbing layer to improve the efficiency. In this paper, morphology formation on the surface of glass substrate was investigated by using HF, mainly classified as random etching and periodic etching. We discussed about the etch mechanism, etch rate and hard mask materials, and periodic light trapping structure.

• 전기의세계
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• v.28 no.9
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• pp.43-50
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• 1979

Silicon nitride films were chemically deposited on silicon substrates by reacting SiCl$_{4}$ and NH$_{3}$ in a nitrogen atmosphere at 700~1100 .deg.C. The deposition rate increased rapidly with deposition temperature upto about 1000 .deg.C, and became less temperature dependent above this temperature. The etch rate of films in buffered HF solution decreased, with an increase of deposition temperature, and a heat treatment at a temperature higher than that of the deposition considerably reduced the etch rate. It indicates that the heat treatment resulted in a densification of the films. Surface charge density of 3~4 * 10$^{11}$ /cm$^{2}$ was determined from the C-V characteristics of MNS diode, and it was also found that surface charge density depended on deposition temperature, but not film thickness. The current-voltage characteristics displayed a logI-V$^{1}$2/ dependence in the temperature range of 300~500.deg.K. Measurement of the slope of this characteristics and its dependence on temperature and bias polarity suggest that conduction in sili con nitride films arises from the Poole-Frenkel mechanism.

• Journal of Integrative Natural Science
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• v.2 no.4
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• pp.275-279
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• 2009

Recently, number of studies for porous silicon (PSi) have been investigated by many researchers. Multistructured porous silicon such as a distributed Bragg reflector (DBR) PSi, has been a topic of interest, because of its unique optical properties. DBR PSi were prepared by using an electrochemical etch of $P{^+}{^+}$-type silicon wafer with resistivity between 0.1 and $10m{\Omega}cm$. The electrochemical etch with square wave current density results in two different refractive indices in the porous layer. In this work, DBR porous silicon chips for a simple and portable organic vapor-sensing device have fabricated. The optical characteristics of DBR PSi have been investigated. DBR porous silicon have been characterized by FT-IR and Ocean optics 2000 spectrometer. The device used DBR PSi chip has been demonstrated as an excellent gas sensor, showing a great senstivity to organic vapor at room temperature.

• Journal of Integrative Natural Science
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• v.7 no.1
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• pp.1-4
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• 2014

Distributed Bragg reflector porous silicon of different characteristics were formed to determine their optical constants in the visible wavelength range using a periodic square wave current between low and high current densities. The surface and cross-sectional SEM images of distributed Bragg reflector porous silicon were obtained using a cold field emission scanning electron microscope. The surface image of distributed Bragg reflector porous silicon indicates that the distributions of pores are even. The cross-sectional image illustrates that the multilayer of distributed Bragg reflector porous silicon exhibits a depth of few microns and applying of square current density during the etching process results two distinct refractive indices in the contrast. Distributed Bragg reflector porous silicon exhibited a porosity depth profile that related directly to the current-time profile used in etch. Its free-standing film was obtained by applying an electro-polishing current.

• ETRI Journal
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• v.17 no.4
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.54-59
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• 1995

We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.29-35
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• 1999

Inductively coupled plsama etching of platinum thin film was studied using $O_2$ addition to $Cl_2$/Ar gas plasma. In this study, Pt etching mechanism was investigated with Ar/$Cl_2$ /$O_2$ gas plasma by using XPS and QMS. Ion current density was measured with Ar/$Cl_2$ /$O_2$ gas plasma by using single Langmuir probe. It was confirmed by using QMS and single Langmuir probe that Cl and Ar species rapidly decreased and ion current density was also decreased with increasing $O_2$ gas ratios. These results implied that the decrease of Pt etch rate is due to the decrease of reactive species ans ion current density with increasing $O_2$ gas mixing ratios. A maximum etch rate of 150nm/min and the oxide selectivity of 2.5 were obtained at Ar/$Cl_2$ /$O_2$ flow rate of 50 seem, RF power of 600 W, dc bias voltage of 125 V, and the total pressure of 10 mTorr.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.83-87
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• 2002

Plasma enhanced chemical vapor deposited (PECVD) silicon nitride ($SiN_X$) is widely used as a gate dielectric material for the hydrogenated amorphous silicon(a-Si:H) thin film transistors (TFT's). We investigated $SiN_X$ films were deposited PECVD at low temperature ($300^{\circ}C$). The reaction gases were used pure nitrogen and a helium diluted of silane gas(20% $SiH_4$, 80% He). Experimental investigations were carried out with the variation of $N_2/SiH_4$ flow ratios from 3 to 50 and the rf power of 200 W. This article presents the $SiN_X$ gate dielectric studies in terms of deposition rate, hydrogen content, etch rate and C-V, leakage current density characteristics for the gate dielectric layer of thin film transistor applications. Electrical properties were analyzed through high frequency (1MHz) C-V and current-voltage (I-V) measurements. The thickness and the refractive index on the films were measured by ellipsometry and chemical bonds were determined by using an FT-IR equipment.

• Applied Chemistry for Engineering
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• v.24 no.5
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• pp.562-565
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• 2013

The high purity Al foil, which has an enlarged surface area by electrochemical etching process, has been used as an anode for an aluminum electrolytic capacitor. Etch pits are randomly distributed on the surface because of the existence of surface irregularities such as impurity and random nucleation of pits. Even though a large surface area was formed on the tunnel-etched Al, its applications to various fields were limited due to non-uniform tunnel morphologies. In this work, the selective electrochemical etching of aluminum was carried out by using a patterned mask fabricated by photolithographic method. The formation of etch pits with uniform distribution has been demonstrated by the optimization of experimental conditions such as current density and etching solution temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.