• 반도체디스플레이기술학회지
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• 제20권3호
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• pp.32-38
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• 2021

We developed an inductively coupled plasma (ICP) etcher for GaN etching using a parallel plasma electrode source with a multifunctional chuck matched to it in order for the low power consumption and low process cost in comparison with the conventional ICP system with a helical-type plasma electrode source. The optimization process condition using it for the micro light-emitting diode (µ-LED) chip fabrication was established, which is an ICP RF power of 300 W, a chuck power of 200 W, a BCl₃/Cl₂ gas ratio of 3:2. Under this condition, the mesa structure with the etch depth over 1 ㎛ and the etch angle over 75° and also with no etching residue was obtained for the µ-LED chip. The developed ICP showed the improved values on the process pressure, the etch selectivity, the etch depth uniformity, the etch angle profile and the substrate temperature uniformity in comparison with the commercial ICP. The µ-LED chip fabricated using the developed ICP showed the similar or improved characteristics in the L-I-V measurements compared with the one fabricated using the conventional ICP method

• Korean Chemical Engineering Research
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• 제43권4호
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• pp.531-536
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• 2005

포토리지스트 마스크로 패턴된 CoTb 및 CoZrNb 자성 박막에 대한 유도 결합 플라즈마 반응성 이온 식각이 $Cl_2/Ar$와 $C_2F_6/Ar$ 가스를 이용하여 진행되었고 식각 속도와 식각 프로파일 측면에서 조사되었다. $Cl_2$와 $C_2F_6$ 가스의 농도가 증가함에 따라서 자성 박막들의 식각 속도는 감소하였고 식각 경사는 낮아졌다. 자성 박막들의 식각 가스로서 $Cl_2/Ar$이 빠른 식각 속도와 가파른 식각 경사를 얻는데 있어서 $C_2F_6/Ar$ 보다 더 효과적이었다. Coil rf power의 증가는 플라즈마 내의 Ar 이온과 라디칼의 밀도를 증가시키고 dc bias voltage의 증가는 기판으로 스퍼터되는 Ar 이온의 에너지를 증가시키기 때문에 coil rf power와 dc bias voltage가 증가할수록 식각 속도와 식각 경사는 증가하였지만 패턴의 측면에서 재증착이 일어났다. 자성 박막들의 적층으로 형성된 magnetic tunnel junction stack에 고밀도 플라즈마 반응성 이온 식각을 적용하여, 높은 식각 경사와 재증착이 없는 깨끗한 식각 프로파일을 얻었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.80-81
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• 2012

Recently, one of the critical issues in the etching processes of the nanoscale devices is to achieve ultra-high aspect ratio contact (UHARC) profile without anomalous behaviors such as sidewall bowing, and twisting profile. To achieve this goal, the fluorocarbon plasmas with major advantage of the sidewall passivation have been used commonly with numerous additives to obtain the ideal etch profiles. However, they still suffer from formidable challenges such as tight limits of sidewall bowing and controlling the randomly distorted features in nanoscale etching profile. Furthermore, the absence of the available plasma simulation tools has made it difficult to develop revolutionary technologies to overcome these process limitations, including novel plasma chemistries, and plasma sources. As an effort to address these issues, we performed a fluorocarbon surface kinetic modeling based on the experimental plasma diagnostic data for silicon dioxide etching process under inductively coupled C4F6/Ar/O2 plasmas. For this work, the SiO2 etch rates were investigated with bulk plasma diagnostics tools such as Langmuir probe, cutoff probe and Quadruple Mass Spectrometer (QMS). The surface chemistries of the etched samples were measured by X-ray Photoelectron Spectrometer. To measure plasma parameters, the self-cleaned RF Langmuir probe was used for polymer deposition environment on the probe tip and double-checked by the cutoff probe which was known to be a precise plasma diagnostic tool for the electron density measurement. In addition, neutral and ion fluxes from bulk plasma were monitored with appearance methods using QMS signal. Based on these experimental data, we proposed a phenomenological, and realistic two-layer surface reaction model of SiO2 etch process under the overlying polymer passivation layer, considering material balance of deposition and etching through steady-state fluorocarbon layer. The predicted surface reaction modeling results showed good agreement with the experimental data. With the above studies of plasma surface reaction, we have developed a 3D topography simulator using the multi-layer level set algorithm and new memory saving technique, which is suitable in 3D UHARC etch simulation. Ballistic transports of neutral and ion species inside feature profile was considered by deterministic and Monte Carlo methods, respectively. In case of ultra-high aspect ratio contact hole etching, it is already well-known that the huge computational burden is required for realistic consideration of these ballistic transports. To address this issue, the related computational codes were efficiently parallelized for GPU (Graphic Processing Unit) computing, so that the total computation time could be improved more than few hundred times compared to the serial version. Finally, the 3D topography simulator was integrated with ballistic transport module and etch reaction model. Realistic etch-profile simulations with consideration of the sidewall polymer passivation layer were demonstrated.

• 한국진공학회지
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• 제20권5호
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• pp.322-326
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• 2011

상부 전극에 RF power 가 직접 인가되는 capacitively coupled plasma source를 이용한 oxide layer etching 공정은 현재 반도체 제조 공정에서 매우 유용하게 사용되고 있는 방식이다. 그러나 디바이스의 사이즈가 점점 작아지면서 공정을 진행하기 위한 RF power도 커지고, plasma ignition 되는 electrode 사이의 간격도 점점 좁아지는 기술적 변화가 이루어지고 있다. 이러한 H/W의 변화에 따라 예상치 못한 문제들로 공정을 적용하는데 많은 문제점이 발생하고 있는데, 공정 진행 시에 plasma의 영향으로 인한 electrode의 온도 변화도 그 중 하나이다. 이러한 온도 변화로 인해 wafer to wafer의 공정 진행 결과가 서로 다르게 나타나게 하는 문제가 야기되고 있다. 아래의 내용에서는 상부 electrode의 온도 변화에 따른 etch 특성을 연구하고, 이를 개선할 수 있는 방법에 대해 논하고자 한다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.408-408
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• 2012

It is well known that magnetic random access memory (MRAM) is nonvolatile memory devices using ferromagnetic materials. MRAM has the merits such as fast access time, unlimited read/write endurance and nonvolatility. Although DRAM has many advantages containing high storage density, fast access time and low power consumption, it becomes volatile when the power is turned off. Owing to the attractive advantages of MRAM, MRAM is being spotlighted as an alternative device in the future. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal- oxide semiconductor (CMOS). MTJ stacks are composed of various magnetic materials. FePt thin films are used as a pinned layer of MTJ stack. Up to date, an inductively coupled plasma reactive ion etching (ICPRIE) method of MTJ stacks showed better results in terms of etch rate and etch profile than any other methods such as ion milling, chemical assisted ion etching (CAIE), reactive ion etching (RIE). In order to improve etch profiles without redepositon, a better etching process of MTJ stack needs to be developed by using different etch gases and etch parameters. In this research, influences of $O_2$ gas on the etching characteristics of FePt thin films were investigated. FePt thin films were etched using ICPRIE in $CH_4/O_2/Ar$ gas mix. The etch rate and the etch selectivity were investigated in various $O_2$ concentrations. The etch profiles were studied in varying etch parameters such as coil rf power, dc-bias voltage, and gas pressure. TiN was employed as a hard mask. For observation etch profiles, field emission scanning electron microscopy (FESEM) was used.

• 공업화학
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• 제17권3호
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• pp.327-330
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• 2006

Si nanodot 배열을 형성하기 위하여 $NbO_{x}$ nanopillar를 건식식각 공정의 식각마스크로써 이용하기 위한 가능성이 조사되었다. $NbO_{x}$ nanopillar는 Al과 Nb의 양극산화 공정을 이용하여 준비되었다. $NbO_{x}$ nanopillar의 식각속도와 식각프로파일은 고밀도 플라즈마를 이용한 반응성 이온 식각법에 의해서 식각가스의 농도와 coil rf power, 그리고 dc bias voltage를 각각 변화시키면서 조사 되었다. $Cl_{2}$ 가스의 농도가 증가할수록 $NbO_{x}$ nanopillar의 식각속도는 감소하였고 coil rf power와 dc bias voltage의 증가는 식각속도의 상승을 초래했다. 선택된 식각조건에서 식각시간을 변화하여 $NbO_{x}$ nanopillar의 식각특성 및 식각메커니즘이 조사되었다.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.53-58
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• 2022

Shape changes of hard mask play a key role in the aspect ratio dependent etch (ARDE). For etch process using high density and energy ions, deformation of hard mask shape becomes more severe, and high aspect ratio (HAR) etch profile is distorted. In this study, polygonal geometric model for shape-deformation of amorphous carbon layered hard mask is suggested to control etch profile during the process. Mask shape is modeled with polygonal geometry consisting of trapezoids and rectangles, and it provides dynamic information about angles of facets and etched width and height of remained mask shape, providing important features for real-time HAR etch profiling.

• Transactions on Electrical and Electronic Materials
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• 제16권6호
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• 반도체디스플레이기술학회지
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• 제2권3호
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• pp.7-11
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• 2003

In this research, the etching characteristics of via contact and deep contact hole have been studied using multi-pole inductively coupled plasma(MICP) etching system. We investigated Plasma density of MICP source using the Langmuir probe and etching characteristics with RF frequency, wall temperature, chamber gap, and gas chemistry containing Carbon and Fluorine. As the etching time increases, formation of the polymer increases. To improve the polymer formation, we controlled the temperature of the reacting chamber, and we found that temperature of the chamber was very effective to decrease the polymer thickness. The deep contact etch profile and high selectivity(oxide to photoresist) have been achieved with the optimum mixed gas ratio containing C and F and the temperature control of the etching chamber.

• 한국진공학회지
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• 제7권2호
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• pp.155-160
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• 1998

256M DRAM급에 해당하는 0.25$\mu\textrm{m}$의 회로선 폭을 가공하기 위해 Arc layer & DUV resist 사용이 필수적이다. Poly-Si 식각시 Arc layer 적용여부 및 resist 종류에 따른 차이 를 TCP-9408 etcher(Lam Research Co.)에서 $Cl_2/O_2, Cl_2/N_2, Cl_2$/HBr 3가지 gas chemistry 를 변화시키면서 조사하였다. 동일한 식각 조건에서 DUV resist사용의 경우에 I-line resist 에 비해 식각 profile이 profile이 positive하고 CD gain도 크게 나왔다. 이것은 resist손실에 의한 polymer생성의 증가가 식각시 측벽 보호막을 강화시키기 때문이다. Arc layer 적용의 경우 Arc layer 식각시 생기는 fluorine계 polymer가 poly-Si 식각시 mask역할을 하므로 CD gain이 증가하는 것으로 나타났다. Gas chemistry에 의한 영향은 $Cl_2/O_2$의 경우가 식각 시 polymer형성을 촉진시켜 positive profile 및 CD gain을 초래하였다. $Cl_2$/HBr의 경우에는 profile이 vertical 하였고 CD gain도 거의 없었다. 또한 dense pattern 과 isolated pattern 사이의 profile 및 CD 차이도 가정 작게 나타났다. HBr gas 사용이 식각시 pattern density 에 따른 측벽 보호막 형성의 불균일성을 최소화 시켜 양호한 특성을 보여주었다.