• 한국군사과학기술학회지
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• 제3권1호
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• pp.116-126
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• 2000

Turbo codes are the most exciting and potentially important development in coding theory in recent years. They were introduced in 1993 by Berrou, Glavieux and $Thitimajshima,({(1)}$ and claimed to achieve near Shannon-limit error correction performance with relatively simple component codes and large interleavers. A required Eb/N0 of 0.7㏈ was reported for BER of $10^{-5}$ and code rate of $l/2.^{(1)}$ However, to implement the turbo code system, there are various important details that are necessary to reproduce these results such as AGC gain control, optimal wordlength determination, and metric rescaling. Further, the memory required to implement MAP-based turbo decoder is relatively considerable. In this paper, we confirmed the accuracy of these claims by computer simulation considering these points, and presented a optimal wordlength for Turbo code design. First, based on the analysis and simulation of the turbo decoder, we determined an optimal wordlength of Turbo decoder. Second, we suggested the MAP decoding algorithm based on sliding-window method which reduces the system memory significantly. By computer simulation, we could demonstrate that the suggested fixed-point Turbo decoder operates well with negligible performance loss.

• 대한전자공학회논문지SD
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• 제49권1호
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• pp.25-34
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• 2012

본 논문은 고속 WPAN 시스템에 대한 가변 길이 8-병렬 리드-솔로몬(RS) 복호기에 관한 일반적인 구조를 제안한다. 제안된 구조는 RS(255,239) 코드뿐만 아니라 다양한 단축화 RS 부호들을 지원 할 수 있다. 특히, 가변길이 구조는 다양한 단축화 RS 부호에 대해 가변적인 낮은 지연을 제공하며, 8-병렬 구조를 적용하여 높은 데이터 처리율을 제공한다. 제안된 RS 복호기는 90-$nm$ CMOS 표준 셀 기술을 사용하여 성능 분석을 수행하였고, 클록 주파수 300$MHz$에서 19-$Gbps$ 데이터 처리율을 제공한다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제4권1호
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• pp.62-77
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• 2010

Emerging applications with high data rates will need to transport bulk data reliably in wireless sensor networks. ARQ (Automatic Repeat request) or Forward Error Correction (FEC) code schemes can be used to provide reliable transmission in a sensor network. However, the naive ARQ approach drops the whole frame, even though there is a bit error in the frame and the FEC at the bit level scheme may require a highly complex method to adjust the amount of FEC redundancy. We propose a bulk data transmission scheme based on erasure-resilient code in this paper to overcome these inefficiencies. The sender fragments bulk data into many small blocks, encodes the blocks with LT codes and packages several such blocks into a frame. The receiver only drops the corrupted blocks (compared to the entire frame) and the original data can be reconstructed if sufficient error-free blocks are received. An incidental benefit is that the frame error rate (FER) becomes irrelevant to frame size (error recovery). A frame can therefore be sufficiently large to provide high utilization of the wireless channel bandwidth without sacrificing the effectiveness of error recovery. The scheme has been implemented as a new data link layer in TinyOS, and evaluated through experiments in a testbed of Zigbex motes. Results show single hop transmission throughput can be improved by at least 20% under typical wireless channel conditions. It also reduces the transmission time of a reasonable range of size files by more than 30%, compared to a frame ARQ scheme. The total number of bytes sent by all nodes in the multi-hop communication is reduced by more than 60% compared to the frame ARQ scheme.

• 한국통신학회논문지
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• 제25권11B호
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• pp.1864-1871
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• 2000

본 논문에서는 차세대 무선 통신 시스템에 적용이 가능한 새로운 FEC(Forward Error Correction) 부호화 방법으로 MLC(Multi-Level Convolutional) 부호화 방식을 제안한다. 차세대 무선통신서비스는 음성, 데이터, 영상 등 많은 종류의 서비스를 함으로써 데이터의 처리속도가 빠른 시스템이 요구된다. 데이터 처리시간을 단축시키기 위한 방법으로 다중 레벨을 이용하여 부호어를 만들어 내는 방식의 부호화 시스템을 설계하였다. MLC는 부호 처리시간을 단축시킬 뿐만 아니라 다양한 알고리즘을 이용해 부호어를 만들어 낼 수 있다는 특징을 가지게 된다. 모의실험은 MLC 코드의 두 가지 방법, Modulo- operation 방식과 Galois Field-Operation 방식을 이용하여 수행하였다. 또한 모의실험을 통하여 (s=2, T=2)인 경우가 MLC 부호기의 최적 연결다항식임을 알았다.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.69-72
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• 2005

As life style becomes to be complicated, lots of support technologies were developed. The bar code technology is one of them. It was renovating approach to goods industry. However, data storage ability in one dimension bar code came in limit because of industry growth. Two-dimension bar code was proposed to overcome one-dimension bar code. PDF417 bar code most commonly used in standard two-dimension bar codes is well defined at data decoding and error correction area. More works could be done in bar code image acquisition process. Applying various image enhancement algorithms, the recognition rate of PDF417 bar code is improved.

• 한국멀티미디어학회논문지
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• 제9권6호
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• pp.728-734
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• 2006

Carrier interferometry code is considered as a promising scheme that provides significant performance improvement via frequency diversity effect. Space-time coding is commonly employed to achieve a performance gain through space diversity. The combination of these techniques and forward error correction coding will lead to enhanced system capacity and performance. This paper presents a low-density parity check (LDPC) coded space-time orthogonal frequency division multiplexing (OFDM) transmission scheme with carrier interferometry code for high-capacity and high-performance mobile multimedia communications. Computer simulations demonstrate that the proposed mobile multimedia transmission system offers a considerable performance improvement of approximately 9dB in terms of Eb/No in the Rayleigh fading channel with relatively low delay spread, in comparison with space-time OFDM. Performance gains are further increased, comparing with traditional OFDM systems.

• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 2006년도 춘계 국제학술대회 논문집
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• pp.143-147
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• 2006

Wireless sensor networks(WSN) technology has various applications such as surveillance and information gathering in the uncontrollable area of human. One of major issues in WSN is the research for reducing the energy consumption and reliability of data. A system with forward error correction(FEC) can provide an objective reliability while using less transmission power than a system without FEC. In this paper, we propose to use LDPC codes of various code rate(0.53, 0.81, 0.91) for FEC for WSN. Also, we considered node-to-node interference in addition to AWGN channel. The proposed system has not only high reliable data transmission at low SNR, but also reduced transmission power usage.

• 제어로봇시스템학회논문지
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• 제12권8호
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• pp.765-772
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• 2006

The L2 Civil Signal (L2CS) will be transmitted by modernized IIR(IIR-M), IIF and all subsequent GPS satellites. It contains two codes of different length; CM code contains 10,230chips, repeats every 20milliseconds and is modulated with message data, and CL code contains 767,250chips, repeats every 1.5second Z-count and has no data modulation. And the message data is encoded for Forward Error Correction(FEC). The long code length is useful for weak signal, but it also requires very long acquisition time. Therefore, the structure of GPS Ll/L2C Correlator and the fast acquisition scheme are proposed in this paper.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2011년도 추계학술발표대회
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• pp.1166-1169
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• 2011

In this paper, we design a Circle dot Code, In our scheme, we design a dot patterns for increasing maximum capacity and also for increasing robustness to Affine Transformation. Our code Can be extended according number of data circle. We use three data circle vision code. In this type code, after acquiring camera images for the Circle dot Codes, and perform error correction decoding using four position symbols and six CRC symbols. We perform graph based dot code analysis which determines the topological distance between dot pixels. Our code can be bridged the real world and ubiquitous computing environment.

• 대한전자공학회논문지SD
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• 제42권2호
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• pp.23-30
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• 2005

이 논문에서는 낮은 stand-by power 및 DLL의 재동작 후 fast relocking 구조를 가지는 저전력, 고속 VISI 칩용 DLL(지연 고정 루프) 기반의 다중 클락 발생기를 제안하였다. 제안된 구조는 주파수 곱셈기를 이용하여 주파수 체배가 가능하며 시스템 클락의 듀티비에 상관없이 항상 50:50 듀티비를 위한 Duty-Cycle Correction 구조를 가지고 있다. 또한 DAC를 이용한 디지털 컨트롤 구조를 클락 시스템이 standby-mode에서 operation-mode 전환 후 빠른 relocking 동작을 보장하고 아날로그 locking 정보를 레지스터에 디지털 코드로 저장하기 위해 사용하였다. 클락 multiplication을 위한 주파수 곱셈기 구조로는 multiphase를 이용한 feed-forward duty correction 구조를 이용하여 지연 시간 없이 phase mixing으로 출력 클락의 duty error를 보정하도록 설계하였다. 본 논문에서 제안된 DLL 기반 다중 클락 발생기는 I/O 데이터 통신을 위한 외부 클락의 동기 클락과 여러 IP들을 위한 고속 및 저속 동작의 다중 클락을 제공한다. 제안된 DLL기반의 다중 클락 발생기는 $0.35-{\mu}m$ CMOS 공정으로 $1796{\mu}m\times654{\mu}m$ 면적을 가지며 동작 전압 2.3v에서 $75MHz\~550MHz$ lock 범위와 800 MHz의 최대 multiplication 주파수를 가지고 20psec 이하의 static skew를 가지도록 설계되었다.