• Journal of the Korean Institute of Intelligent Systems
• /
• v.18 no.5
• /
• pp.611-616
• /
• 2008

Error correcting codes (ECCs) are commonly used to protect against the soft errors. Single error correcting and double error detecting (SEC-DED) codes are generally used for this purpose. The proposed approach in this paper selectively reduced power consumption, delay, and area in single-error correcting, double error-detecting checker circuits that perform memory error correction. The multi-objective genetic algorithm is employed to solve the non -linear optimization problem. The proposed method allows that user can choose one of different non-dominated solutions depending on which consideration is important among them. Because we use multi-objective genetic algorithm, we can find various dominated solutions. Therefore, we can choose the ECC according to the important factor of the power, delay and area. The method is applied to odd-column weight Hsiao code which is well- known ECC code and experiments were performed to show the performance of the proposed method.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.30 no.5
• /
• pp.781-793
• /
• 2020

In this paper, we propose a new RLWE-based scheme named μ-Hope that exploits Error Correcting Code(ECC) on NewHope. The previous parameters of NewHope uses 12289 as a prime modulus, and the size of the public key, private key, and ciphertext is 928-byte, 1888-byte, and 1120-byte respectively, which can be said to be larger than other RLWE based algorithms. In this paper, we propose μ-Hope, which changes modulus 12289 to 769 to reduce the size of the public key, private key, and ciphertext. Also, we adopts XE1 as an Error Correcting Code(ECC) to solve the increased decryption failure rate caused by using a small prime modulus. As a result, the size of the public key, private key, and ciphertext decreased by 38%, 37%, and 37% respectively. As the computational efficiency caused by using a small prime modulus exceeds the performance degradation by exploiting ECC, this result in 25% performance improvement for a single key exchange.

• ETRI Journal
• /
• v.30 no.6
• /
• pp.799-806
• /
• 2008

In this paper, a new design for an error correcting code (ECC) is proposed. The design is aimed to build an ECC circuitry with minimal power consumption. The genetic algorithm equipped with the symbiotic mechanism is used to design a power-efficient ECC which provides single-error correction and double-error detection (SEC-DED). We formulate the selection of the parity check matrix into a collection of individual and specialized optimization problems and propose a symbiotic evolution method to search for an ECC with minimal power consumption. Finally, we conduct simulations to demonstrate the effectiveness of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.11
• /
• pp.1626-1634
• /
• 1993

In this paper we propose a coding scheme which combines source codes and error correcting codes in order to be robus to channel noise. One of the coding schemes that take into account both the source and the channel is the channel optimized quantizer (COQ) which simultaneously minimizes quantization noise and the noise due to channel errors. This paper deals with the problem of combining channel optimized quantizers with ECC to build an improved system. To be specific, we computed the performance of an n bit COQ and that of an n-1 bit COQ followed by an (n-1)/n punctured convolutional code. From this result whether or not the ECC are selected is determined by the number of allocated bits and the channel bit error rate. These results are applied to the image trans-mission method using DCT, and the system performances are evaluated.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.9
• /
• pp.1180-1186
• /
• 2020

One of the Embedded systems Tiny Processing Unit (TPU) usually acts in harsh environments like external shock or insufficient power. In these cases, data could be polluted, and cause critical problems. As a solution to data pollution, many embedded systems are using Error Correcting Code (ECC) to protect and restore data. However, ECC processing in TPU increases the overall processing time by increasing the time of instruction fetch which is the bottleneck. In this paper, we propose an architecture of parallelized ECC block to the reduce bottleneck of TPU. The proposed architecture results in the reduction of time 10% compared to the original model, although memory usage increased slightly. The test is evaluated with a matrix product that has various instructions. TPU with proposed parallelized ECC block shows 7% faster than the original TPU with ECC and was able to perform the proposed test accurately.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.19 no.2
• /
• pp.180-184
• /
• 2009

The memory is very sensitive to the soft error because the integration of the memory increases under low power environment. Error correcting codes (ECCs) are commonly used to protect against the soft errors. This paper proposes a new genetic ECC design method which reduces power consumption. Power is minimized using the degrees of freedom in selecting the parity check matrix of the ECCs. Therefore, the genetic algorithm which has the novel genetic operators tailored for this formulation is employed to solve the non-linear power optimization problem. Experiments are performed with Hamming code and Hsiao code to illustrate the performance of the proposed method.

• Convergence Security Journal
• /
• v.11 no.6
• /
• pp.37-44
• /
• 2011

VANET(Vehicular Ad-hoc Network) is a kind of ad hoc networks consist of intelligence vehicular ad nodes, and has become a hot emerging research project in many field. It provide traffic safety, cooperative driving and etc. but has also some security problems that can be occurred in general ad hoc networks. Also, in VANET, vehicles shoul d be able to authenticate each other to securely communicate with network-based infrastructure, and their locations and identifiers should not be exposed from the communication messages. This paper proposes V2I(Vehicular to Infra structure) authentication protocol that anonymity and untraceability of vehicular using Error Correcting Code that ge nerate encoding certification using generation matrix. The proposed scheme based on ECC resolves overhead problems of vehicular secure key management of KDC.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.1
• /
• pp.43-49
• /
• 2008

In this paper, a method using the Ant Colony Optimization(ACO) is proposed for reducing the power consumption of memory ECC checker circuitry which provide Single-Error Correcting and Double-Error Detecting(SEC-DED). The H-matrix which is used to generate SEC-DED codes is optimized to provide the minimum switching activity with little to no impact on area or delay using the symmetric property and degrees of freedom in constructing H-matrix of Hsiao codes. Experiments demonstrate that the proposed method can provide further reduction of power consumption compared with the previous works.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.3C
• /
• pp.195-204
• /
• 2007

The cyclic redundancy check(CRC) code used to decide retransmission request in hybrid automatic repeat request(HRAQ) system can also be used to stop iterative decoding of turbo code if it is used as an error correcting code(ECC) of HARQ system. Thus a scheme to use CRC code for both iteration stop and repeat request in the HARQ system with turbo code based on the standard of cdma 2000 system is proposed in this paper. At first, the optimum CRC code which has the minimum length without performance degradation due to undetected errors is found. And the most appropriate turbo encoder structure is also suggested. As results, it is shown that at least 32-bit CRC code should be used and a turbo code with 3 constituent encoders is considered to be the most appropriate one.

• The Journal of the Korea Contents Association
• /
• v.16 no.10
• /
• pp.477-482
• /
• 2016

This paper presents a new method of parity storing for ECC(error correcting code) in SSD (solid-state drive) and suitable structure of the controller. In general usage of NAND flash memory, we partition a page into data and spare area. ECC parity is stored in the spare area. The method has overhead on area and timing due to access of the page memory discontinuously. This paper proposes a new parity policy storing method that reduces overhead and R(read)/W(write) timing by using whole page area continuously without partitioning. We analyzed overhead and R/W timing. As a result, the proposed parity storing has 13.6% less read access time than the conventional parity policy with 16KB page size. For 4GB video file transfer, it has about a minute less than the conventional parity policy. It will enhance the system performance because the read operation is key function in SSD.