• ETRI Journal
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• v.46 no.3
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.215-223
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• 2003

Turbo codes are selected as FEC(Forward error correction) codes with convolution code in 3GFP(3rd generation partnership project) and 3GPP2 standard of IMT2000. Especially, l/3 turbo code with K=4 is employed for 3GPP standard. In this paper, we proposed a hardware structure of a turbo decoder and denveloped the decoder for 3GPP standard turbo code. For its efficient operation, we design a SOVA decoder by employing a register exchange decoding block and new path metric normalization block as a SISO constituent decoder. In addition, we estimate its performance under MATLAB 6.0 and designed the turbo decoder including control block, input control buffer, SOVA constituent decoder with VHDL. Finally, we synthesized the developed turbo decoder under Synopsys FPGA Express and verified it with ALTERA EPF200SRC240-3 FPGA device.

• Journal of the Korea Convergence Society
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• v.10 no.12
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• pp.251-255
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• 2019

The QR codes are printed in sticker form and have many advantages in terms of location recognition accuracy or installation cost compared to the location recognition method, which attaches artificial indicators to ceilings or walls for low-cost location recognition, and the way in which the location is recognized by vision, to create robots that are generally applicable to all industries. In this study, it is shown that the two-dimensional square bar code applied to the robot within 3 mm of error allows the robot to be made with high accuracy and accurate location control. In particular, the fusion research, combined with various engineering technologies, describes QR code-aware indoor mobile robot control research centered on the construction of the system.

• ETRI Journal
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• v.37 no.1
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• pp.186-196
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• 2015

In resource-constrained, low-cost, radio-frequency identification (RFID) sensor-based mobile ad hoc networks (MANETs), ensuring security without performance degradation is a major challenge. This paper introduces a novel combination of steps in lightweight protocol integration to provide a secure network for RFID sensor-based MANETs using error-correcting codes (ECCs). The proposed scheme chooses a quasi-cyclic ECC. Key pairs are generated using the ECC for establishing a secure message communication. Probability analysis shows that code-based identification; key generation; and authentication and trust management schemes protect the network from Sybil, eclipse, and de-synchronization attacks. A lightweight model for the proposed sequence of steps is designed and analyzed using an Alloy analyzer. Results show that selection processes with ten nodes and five subgroup controllers identify attacks in only a few milliseconds. Margrave policy analysis shows that there is no conflict among the roles of network members.

• Journal of the Korean Society for information Management
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• v.7 no.1
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• pp.24-39
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• 1990

Many factors play a role in designing the interface for bibliographic data entry system in response to the various needs. Among the major variables to be considered are planning, record format screen design, automatic generation of access points, error chocking, download from bibliographic databases, character codes, card catalog production, and use of authority data. This paper described with examples how these design considerations can be implemented in empirical system.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.11b
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• pp.557-560
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• 2003

In this paper, we developed an editor and running engine for the SoftPLC. LD is the most popular standard IEC 1131-3 PLC language in Korea and used over 90% among the 5 PLC languages. In this paper, we have developed the ISPLC(Intelligent Agent System based Software Programmable Logic Controller). In ISPLC system, LD programmed by a user is converted to IL, which is one of intermediate codes, and IL is converted to the standard C code which can be used in a commercial editor such as visual C++. In ISPLC, the detection of logical error in high level programming(C) is more efficient than PLC programming itself. ISPLC provide easy programming platform to such beginner as well as professionals. The study of code conversion of LD-> U->C is firstly tried in the world as well as KOREA.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.132-137
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• 2007

Jacket transforms are a class of transforms which are simple to calculate, easily inverted and are size-flexible. Previously reported jacket transforms were generalizations of the well-known Walsh-Hadamard transform (WHT) and the center-weighted Hadamard transform (CWHT). In this paper we present a new class of jacket transform not derived from either the WHT or the CWHT. This class of transform can be applied to any even length vector, and is applicable to finite fields and is useful for constructing error control codes.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2002.04a
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• pp.53-60
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• 2002

It has been recognized that damage control must become a more explicit design consideration. In an effort to develop design methods based on performance it is clear that the evaluation of the inelastic response is required. The methods available to the design engineer today are nonlinear time history analyses, or monotonic static nonlinear analyses, or equivalent static analyses with simulated inelastic influences. Some codes proposed the capacity spectrum method based on the nonlinear static(pushover) analysis to determine earthquake-induced demand given the structure pushover curve. This procedure is conceptually simple but iterative and time consuming with some errors. This paper presents a nonlinear direct spectrum method to evaluate seismic Performance of structure, without iterative computations, given the structural initial elastic period and yield strength from the pushover analysis, especially for multi degree of freedom structures. The purpose of this paper is to investigate accuracy and confidence of this method from a point of view of various earthquakes and unloading stiffness degradation parameters.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.8-14
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• 2013

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1155-1160
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• 2017

This paper describes a system implementation for the automatic inspection on the ventilating electronic device based on the reliability improvement. To be enhancement, the inspection error is minimized by the automatic inspection system on the ventilating apparatuses against the manual inspecting system. The system consists of the control system, software structure and monitoring system to be scanning the inspection processing. The inspection system for reliability improvement is evaluated in Gage Repeatability and Reproducibility. The experimental results are improved about 2 times inspecting speed, measured error ${\pm}0.02V$, effectiveness of discriminating performance 15%, missing probability 17% and false alarm probability 12% respectively in comparing with the manual inspection based on the wind pressure sensor. The system will be also improved more by making database and product bar codes for the total quality control system to the effective reliability enhancement in the future.