• 전력전자학회논문지
• /
• 제20권6호
• /
• pp.526-533
• /
• 2015

A new algorithm is proposed for the estimation of equivalent grid impedance at the point of common coupling of a grid-tie inverter output. The estimated impedance parameter can be used for the improvement of the performance and the stability of the distributed generation system. The estimation error is inevitable in the conventional estimation method because of the axis rotation due to PLL. In the conventional estimation error, the d-q voltage and current are used for the calculation of the impedance with active and reactive current injections. Conversely, in the proposed algorithm, the negative sequence current is injected, and then the negative sequence voltage is measured for the impedance estimation. As the positive and negative sequence current controller is independent and the PLL is based on the positive sequence component only, the estimation of the equivalent impedance can be achieved with high accuracy. Simulation and experimental results are compared to validate the proposed algorithm.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권2호
• /
• pp.114-126
• /
• 2013

In this paper, we present a set of methodologies to model the electromagnetic susceptibility (EMS) testing of I/O buffers for mobile system memory based on the bulk current injection (BCI) method. An efficient equivalent circuit model is developed for the current injection probe, line impedance stabilization network (LISN), printed circuit board (PCB), and package. The simulation results show good correlation with the measurements and thus, the work presented here will enable electromagnetic susceptibility analysis at the integrated circuit (IC) design stage.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 제36회 하계학술대회 논문집 A
• /
• pp.332-334
• /
• 2005

This paper presents a dynamic simulation of the unified power flow controller (UPFC) using a current injection method. Flexible AC Transmission System (FACTS) devices give more flexibility of control for security and economic operation of power systems. Diffculties of modeling UPFC in the conventional dynamic simulation programs arise from the fact that the injected voltage by the series inverter is superimposed on the shunt inverter side voltage. A solution can be a current injection method, in which a serial part of UPFC is converted to a parallel equivalent circuit using source transformation, and two current sources affect each other at every time step. To verify efficiency of this method, the proposed model is applied for the transient analysis of an example power system.

• Journal of Electrical Engineering and Technology
• /
• 제11권6호
• /
• pp.1582-1589
• /
• 2016

In this paper the integration of Distributed Generation (DG) in radial distribution system is investigated by computing the optimal site and size of DG to be placed. An analytical expression based on equivalent current injection has been derived by utilizing topological structure of radial distribution system to find optimal size of DG to minimize losses. In the presented formulation, the optimal DG placement is obtained without repeatedly computing the load flow. The proposed formulation can be used to find the optimal size of all types of DGs namely Type-I, Type-II, Type-III and Type-IV DGs. The investigations are carried out on IEEE 33-bus and 69-bus radial distribution systems. The optimal DG placement results into reduction in active and reactive power losses and improvement in voltage profile of the buses.

• 한국전자파학회논문지
• /
• 제24권4호
• /
• pp.436-447
• /
• 2013

본 논문에서는 IC(Integrated Circuit) 전자파 전도내성 시험 방법인 BCI(Bulk Current Injection)와 DPI(Direct Power Injection)를 이용하여 1.8 V I/O 버퍼에 대한 IC 전자파 전도내성을 시험하였다. IC 전자파 전도내성 시험을 회로 해석기를 사용하여 시뮬레이션 할 수 있는 등가회로 모델(model)을 개발하고 검증하였다. BCI와 DPI의 주파수에 따른 forward 전력을 비교한 결과는 주파수 성분에 따라 실제 IC에 도달하는 전자파(electromagnetic, EM) 노이즈의 양이 제한됨을 보여준다. 시뮬레이션을 통해, 가해지는 RF(Radio Frequency) 노이즈가 전달되는 경로의 삽입손실을 구하여, 하나의 시험 방법만으로는 넓은 주파수 영역에서 실질적인 IC 전자파 내성시험의 어려움을 발견하였다. 따라서 규정된 시험 방법을 보완하여 넓은 주파수 영역의 노이즈에 대해 신뢰도 높은 IC 전자파 전도내성 시험 방법을 제안한다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권2호
• /
• pp.202-211
• /
• 2014

The bulk current injection (BCI) and direct power injection (DPI) method have been established as the standards for the electromagnetic susceptibility (EMS) test. Because the BCI test uses a probe to inject magnetically coupled electromagnetic (EM) noise, there is a significant difference between the power supplied by the radio frequency (RF) generator and that transferred to the integrated circuit (IC). Thus, the immunity estimated by the forward power cannot show the susceptibility of the IC itself. This paper derives the real injected power at the failure point of the IC using the power transfer efficiency of the BCI method. We propose and mathematically derive the power transfer efficiency based on equivalent circuit models representing the BCI test setup. The BCI test is performed on I/O buffers with and without decoupling capacitors, and their immunities are evaluated based on the traditional forward power and the real injected power proposed in this work. The real injected power shows the actual noise power level that the IC can tolerate. Using the real injected power as an indicator for the EMS test, we show that the on-chip decoupling capacitor enhances the EM noise immunity.

• Advanced Composite Materials
• /
• 제16권1호
• /
• pp.1-10
• /
• 2007

Composite materials consisting of crushed carbon fiber reinforced plastics (CFRP) pieces and acrylonitrile-butadiene-styrene (ABS) resin were prepared by an injection mold method to solve the problem of recycling of CFRP. The electrical properties, such as electrical resistivity, alternating current impedance and electromagnetic interference (EMI) shielding effect, were measured for the composites. The electrical resistivity of the composites showed a percolation type of conduction behavior and no difference between parallel and perpendicular to the injection direction was observed for CFRP content higher than the critical value. Measurement of alternating current impedance revealed that the conduction mechanism is attributed to the direct conductive paths generated by distributed carbon fibers; however, strong frequency dependence of the impedance was observed for the CFRP content near the critical one. The frequency dependence of the impedance is caused by the inter-fiber connection and can be expressed as a simple equivalent circuit. The absorption component of shielding effect (SE) was smaller than the expected value estimated from its resistivity. The decline of SE is thought to be caused by the decrease in effective thickness due to fiber orientation.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1996년도 창립기념 전력전자학술발표회 논문집
• /
• pp.63-66
• /
• 1996

An micro model for the power insulated Gate Bipolar Transistor(IGBT) is developed. The model consistently described the IGBT steady-state current-voltage characteristics and switching transient current and voltage waveform for all loading conditions. The model is based on the equivalent circuit of a MOSFET with supplies the base current to a low-gain, high-level injection, bipolar transistor with its base virtual contact at the collector and of the base. Model results are compared with measured turn-on and turn-off waveform for different drive, load, and feedback circuits.

• 전자공학회논문지
• /
• 제52권11호
• /
• pp.36-43
• /
• 2015

본 연구를 통해서 초점면 배열 이차원 마이크로볼로미터를 위한 픽셀 단위의 신호취득 회로를 연구하였다. 높은 응답도와 긴 적분시간을 갖는 픽셀 단위의 구조를 위해 이 단계 바이어스 전류 억제 방식을 갖는 전류 미러 입력회로를 제안하였다. 제안하는 회로는 $0.35-{\mu}m$ 2-poly 4-metal CMOS 공정을 이용하여 설계했고, 마이크로볼로미터의 배열 크기는 $320{\times}240$이며 픽셀 크기는 $50{\mu}m{\times}50{\mu}m$이다. 제안하는 이 단계 바이어스 전류 억제 방식은 넓은 보정 범위에서 충분히 작은 보정 오차를 보이며, 설계 파라미터를 조정하여 보정 범위와 보정 오차를 간단히 최적화할 수 있다. 제안하는 회로는 높은 응답도와 1 ms 이상의 긴 적분시간을 갖기 때문에 회로의 잡음등가온도차(NETD)를 26 mK까지 개선할 수 있고, 이는 기존회로의 잡음등가 온도차인 67 mK에 비해 매우 개선된 수치이다.

• 전력전자학회논문지
• /
• 제17권6호
• /
• pp.546-552
• /
• 2012

This paper presents an active anti-islanding detection method using negative sequence voltage injection to the grid through a three-phase photovoltaic inverters. Because islanding operation mode can cause a variety of problems, the islanding detection of grid-connected photovoltaic inverter is the mandatory feature. The islanding mode is detected by measuring the magnitude of negative sequence impedance calculated by the negative sequence voltage and current at the point of common coupling. Simulation and experimental test are performed to verify the effectiveness of the proposed method which can detect the islanding mode in the specified time. The test has been done in accordance with the condition on IEEE Std 929-2000.