• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2000년도 추계종합학술대회
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• pp.263-266
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• 2000

In this paper, we formed a transmitter and receiver by using two identical Chua's circuits and then formed wireless transmission line from the channel which was between those two circuits. We proposed a secure communication method in which the desired information signal was synthesized with the chaos signal created in a Chua's circuit and sent to the transmitter through channel. Then the signal was demodulated receiver of Chua's circuit. The method we used to accomplish the sun communication was synthesizing the desired information with the chaos circuit by parallel connection in a wireless transmission line. After transmitting the synthesized signal to the wireless transmission line, we confirmed the actuality of the secure communication by separating the information signal and the chaos signal in the receiver. In order to confirm the security, we compared the wiretapped signal and the recovery signal under the assumption that the wiretapping had taken place. In order to separate the two signals, we transformed the information signal to a current source in the transmitter and detected the current in the receiver.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 추계 기술심포지움 논문집
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• pp.23-27
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• 2000

Simultaneous Switching Noise (SSN) propagated through parallel power and ground planes in high-speed multilayer printed circuit boards (PCBs) causes malfunction of both digital and analog circuits. To reduce SSN, decoupling capacitors are generally used in the PCBs. In this paper, we improve the equivalent circuit model of decoupling capacitor in high-frequency range to analyze the effect of SSN reduction accurately. The analysis is performed by the microwave and RF design system (MDS) method and the finite difference time domain (FDTD) method. We compared the results by the ideal capacitor model with those by the proposed model.

• 전자공학회논문지A
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• 제31A권4호
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• pp.116-126
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• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

• 대한전자공학회논문지
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• 제17권6호
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• pp.93-98
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• 1980

본 논문에서는 conservative 논리회로의 종적접적에 관한 고리를 밝히고 임dml의 3 -3논리회로를 최소한의 소자를 종속하여 실현시키는 문제를 취급하였다. 다만 제 5, 15, 21, 24 및 제29의 5종의 기본유형을 선택하여 이들 중 2개만을 종속함으로써 31종의 전기본유형을 실현시켰다. 본 논문의 함성방향에 있어서는 입출력선의 교우를 허용하였는데 그 상한은 3으로 족하였으며, 합성결과를 표로 요약정리하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2010년도 하계학술대회 논문집
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• pp.9-10
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• 2010

The lighting control power circuits should be designed in stable region according to the environment. A stable circuit is analyzed using ac equivalent circuits. The flyback converter with wide input voltage ranges is suitable for lighting control system. It is designed optimally for stability. The specifications are that the input voltage is 90V-230V, the output power is 12V/2.5A. The stability analysis is established using PSM(Phase Sensitive Multimeter) in experiment. As a result, it is confirmed that the gain margin and the phase margin are in stable area. The validity of the experimental measurement is verified.

• 한국통신학회논문지
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• 제15권1호
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• pp.51-57
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• 1990

입, 출력 정합단에 타원여파기와 보조회로를 첨가하여 광대역증폭기의 마이크로파 집적회로(MIC)를 설계한다. 이 증폭기를 해석하기 위하여 GaAS MESFET의 입, 출력회로를 단방향성 등가회로로 변환한다. 입,출력 임피던스는 타원여파기로 정합하여 집적회로화 한다. 실험결과는 4~8GHz의 주파수내역에서 이득 10.5dB, 최대 정재파비 2.1:1 및 최대 잡음지수 2.5dB의 특성을 보인다.

• Journal of Power Electronics
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• 제16권1호
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• pp.374-387
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• 2016

This paper derives an improved analytical model to estimate switching loss and analyze the effects of parasitic elements on the switching performance of SiC MOSFETs. The proposed analytical model considers the parasitic inductances, the nonlinearity of the junction capacitances and the nonlinearity of the trans-conductance. The turn-on process and the turn-off process are illustrated in detail, and equivalent circuits are derived and solved for each switching transition. The proposed analytical model is more accurate and matches better with experimental results than other analytical models. Note that switching losses calculated based on experiments are imprecise, because the energy of the junction capacitances is not properly disposed. Finally, the proposed analytical model is utilized to account for the effects of parasitic elements on the switching performance of a SiC MOSFET, and the circuit design rules for high frequency circuits are given.

• 대한전자공학회논문지
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• 제14권6호
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• pp.1-5
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• 1977

다이오우드의 비선형특성을 고려하여 트란스레스 이중평형변조제의 입력등가저항 및 동작특성을 정량적으로 고찰하였다. 인력등가저항은 회로의 전력손실 계산식에서 유도하였으며, 반송신호억압 및 변조효율은 다이오우드 회로의 동특성곡선을 나타내는 근사식을 사용하여 계산하였다. 결과식은 다이오우드의 비선형특성 때문에 반송신호전압의 함수로 표시되었다.

• 한국전자파학회지:전자파기술
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• 제5권1호
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• pp.13-21
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• 1994

마이크로스트립 미앤더(meander) 선로를 해석하고 실험하여 저역통과 특성을 고찰하였다. 본 해석방법의 요체는 선로간 상호결합에 관한 해석적인 관계식에 밴드(bend)의 등가모델을 추가한 것이며 이의 수치계산은 빠르고 결합선로의 수에 제한을 받지 않느다. 4중 결합 미앤더 선로에 대한 해석 및 실험 결과들을 제시했으며, 이들이 잘 일치하고 있음을 보였다.

• 조명전기설비학회논문지
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• 제29권7호
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• pp.38-46
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• 2015

This paper propose a variable parameter estimations for variable over current load of five-phase squirrel-cage induction motor(IM) to servo control system. In order to high performance control of AC motor using a field oriented control(FOC) and direct torque control(DTC) algorithm, there are required precise motor parameters for slip calculation, flux observer, controller gain, torque command of current components, rotor position, speed estimation, and so on. We are suggest a analyzed estimation results of the motor parameters that developing five-phase squirrel-cage IM have a stator of concentrated winding for experimental within variable over current load at rated input frequency. There are results of stator winding measurement, no-load test, locked-rotor test, variable over current load test, and estimated parameters of equivalent circuits using manufactured experimental apparatus by IEEE Standard Test Procedure for Polyphase Induction Motors and Generators 112-2004.