• Journal of Engineering Education Research
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• v.17 no.2
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• pp.11-24
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• 2014

The purpose of this study is to develop a teaching-learning model of convergence project based on team teaching. Based on development research methodology which explored a university case, the teaching-learning model was developed including three phases such as preparation, planning, and implementation & evaluation. The preparation phase has three steps as follows: to organize team teaching faculty; to develop convergence projects cooperated by industry and university; and to design instructions based on supporting convergence projects. The last step of preparation phase consists of five design activities of: (1) instructions and teaching contents; (2) communication channel among faculty members; (3) feedback system on students' performance; (4) tools to support learners' activity; and (5) evaluation system. The planning phase has two steps to analyze learners and to introduce and modify instruction and themes of convergence projects. The implementation & evaluation phase includes five steps as bellow: (1) to organize project teams and match teams with faculty members; (2) to do team building and assign duties to students of a team; (3) to provide instruction and consulting to teams; (4) to help teams to conduct projects through creative problem solving; and (5) to design mid-term/final presentation and evaluation. Lastly, the research implications and limitations were discussed for future studies.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.423-424
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• 2008

The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.

• Journal of the Korean Society for Precision Engineering
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• v.1 no.2
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• pp.69-74
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• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2910 "bit-slice" microprocessor chips and 0.5K ROMs of microprogram memory. The system design is an instruction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolatioon speed of (max) 250K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software of the interpolator efficently. In addi- tion to hardware and software design, experimental results are pressented.ressented.

• The Journal of Korean Institute for Practical Engineering Education
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• v.3 no.2
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• pp.142-146
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• 2011

In this paper, to invigorate elderly-friendly industry, a case study on curriculum for re-educational work of the field engineers is introduced. The curriculum has been developed to retrain technicians and engineers in IT-based elderly-friendly business industry, to help them develop elderly-friendly products, and it have been evolved by operating it and analyzing outcome and satisfaction levels since August in 2009. The re-education work of the field engineers are designed for invigorating the IT-based elderly-friendly business industry, based on the instruction system design(ISD) model. To develop IT-based elderly-friendly products, the elderly-friendly accessible design and the elderly-friendly living and health care equipment design are required. For the elderly-friendly accessible design, it consists of "Elderly-Friendly Engineering Based on Human Characteristics", "Color Sensibility and Universal Design for The Elderly", and "Design Understanding and Process". For the elderly-friendly living and health care equipment design, it consists of "Embedded System Design and Debugging Experiments for Elderly-Friendly IT Equipment", "Elderly-Friendly Android Implementation Design", and "Design and Experiments of Silver-care Android-based Smart Equipment".

• Design & Manufacturing
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• v.16 no.3
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• pp.34-38
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• 2022

Regular expression pattern matching is widely used in applications such as computer virus vaccine, NIDS and DNA sequencing analysis. Hardware-based pattern matching is used when high-performance processing is required due to time constraints. ReCPU, SMPU, and REMP, which are processor-based regular expression matching processors, have been proposed to solve the problem of the hardware-based method that requires resynthesis whenever a pattern is updated. However, these processor-based regular expression matching processors inefficiently handle repetitive operations of regular expressions. In this paper, we propose a new instruction set to improve the inefficient repetitive operations of ReCPU and SMPU. We propose REMPi, a regular expression matching processor that enables efficient iterative operations based on the REMP instruction set. REMPi improves the inefficient method of processing a particularly short sub-pattern as a repeat operation OR, and enables processing with a single instruction. In addition, by using a down counter and a counter stack, nested iterative operations are also efficiently processed. REMPi was described with Verilog and synthesized on Intel Stratix IV FPGA.

• Proceedings of the KIEE Conference
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• 2008.10c
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• pp.246-247
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• 2008

Further evolutions of technologies and needs of users will make mobile equipments improved. To make this happen, processor's good performance is essential. Hence, This paper propose a reform of Instruction Execute and Instruction Decode of contemporary ARMv7 which needs low-power and has the high performance for a faster processor. The first chapter explains why the performance of a processor has to be upgraded, the second chapter shows current technologies. The third chapter explains about the proposal and illustrates the structure. Finally, in the forth chapter, the conclusion will be made. 3-way Superscalar, that is proposed in this paper, will make designing a faster processor possible. And it will contribute for the advanced performance of mobile equipments.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.142-148
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• 2008

Though a deblocking filter of H.264/AVC provides enhanced image quality by removing blocking artifact on block boundary, the complex filtering operation on this process is a dominant factor of the whole decoding time. In this paper, we designed an ASIP to accelerate deblocking filter operation with the proposed instruction set. We designed a processor based on a MIPS structure with LISA, simulated a deblocking later model, and compared the execution time on the proposed instruction set. In addition, we generated HDL model of the processor through CoWare's Processor Designer and synthesized with TSMC 0.25um CMOS cell library by Synopsys Design Compiler. As the result of the synthesis, the area and delay time increased 7.5% and 3.2%, respectively. However, due to the proposed instruction set, total execution performance is improved by 18.18% on average.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.366-370
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• 2015

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10b
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• pp.1633-1638
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• 1991

A CAI system is developed to support the Instruction of an aircraft conceptual design for aeronautical engineering students. Three system concepts are proposed and an Object-Oriented approach is applied to construct the system. The system has three major functions to perform a conceptual design: (1) the system stores modular data and empirical formulas used for a wide range of aircraft design tasks from light aircraft to long range airliners. (2) Implementation of modules by message passing makes it easy to realize the various design tasks required for different design requirements. (3) The system allows users to study trade-off among the requirements. The system has a graphical user Interface which allows users to communicate with the system interactively. The effectiveness of the system Is demonstrated through some case studies.