• 한국정보통신학회논문지
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• 제6권2호
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• pp.330-338
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• 2002

소어휘 단어단위의 음성을 인식할 수 있는 음성인식 칩을 설계하였다. 설계된 칩은 음성 신호의 시작과 끝점 검출 부분, LPC 켑스트럼 계수 추출 부분, DTW 실행 부분과 외부 메모리 인터페이스 부분으로 구성되어있다. CMOS 0.35um TLM 공정으로 설계된 이 칩은 4x4mm2의 면적에 126,938개의 게이트로 만들어져 있다. 그리고 전용 H/W의 동작 속도는 5MHz에서 60MHz까지 조정 가능하다. 5MHz 클록을 사용하는 경우, 50∼60 프레임 정도의 소어휘 단어 단위의 음성을 초당 100,000개까지 비교할 수 있는 능력이 있고, 60MHz의 클록을 사용하는 경우는 초당 1,200,000개의 단어를 비교할 수 있다.

• Bulletin of the Korean Chemical Society
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• 제32권7호
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• pp.2377-2384
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• 2011

Azo-acenaphthylene oligomers with repeating acenaphthylene units "n" up to 4, 5, 7, 17 and 19 have been prepared successfully using nitroxide mediated Stable Free Radical Polymerization (SFRP). Azo-acenaphthylene oligomers, reversibly end-capped by the stable nitroxide 2,2,6,6-tetramethyl-1-piperidinoxyl (TEMPO), were further reacted via radical addition to 4-(naphthalenemethoxy)styrene monomer for diblock co-polymer formation. Characterization of the oligomers and diblock co-polymers was accomplished using MALDI-MS supported by GPC (Gel Permeation Chromatography) and $^1H$ NMR spectrometry. MALDI-MS afforded definitive results by providing an inter-peak interval of 152 (m/z), corresponding to acenaphthylene monomer, and inter-peak interval of 260 (m/z) for the naphthalenemethoxystyrene monomer unit in block copolymers. Our study opens the way to control the number of repeat units in the oligomers. Further these oligomers can be tailored with various monomers for the formation of block copolymers.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.579-587
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• 2014

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closed-loop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gain-control block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2008년도 춘계 학술발표회 초청강연 및 논문집
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• pp.1166-1171
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• 2008

Despite of the increasing number of the application of drilled shaft piles in construction site, most studies on pile capacity have been focused on the side shear resistance. But it is common that the drilled shaft is socketed on the rock so as to use its bearing resistance. The prediction of the end movement and characteristics of the bearing capacity of the pile is great important as well. Therefore, a series of scaled model tests were carried out in order to study the characteristics of the bearing capacity on rock mass. The material of the test block was cement mortar which was mixed with sand, cement and water, and the size of a test block size was $240{\times}240{\times}240mm$. The axial load was applied by a miniaturized pile of 45mm in diameter and flat jacks and steel plate were used for confinement to simulate the real underground loading conditions. The relation of load-displacement was measured in various different conditions of rock mass such as strength, discontinuity of the rock mass and in-situ stress, so q-w curves of the end of the pile were presented for each condition.

• 한국정보통신학회논문지
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• 제9권3호
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• pp.647-653
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• 2005

본 논문에서는 캐스코드 결합 HBT의 이미터와 베이스단에 인덕터를 설치하여 저잡음과 고이득 특성을 동시에 나타내는 MMIC-LNA 증폭기를 설계하였다. 제작된 MMIC 증폭단은 3mA, 2.7V의 바이어스 조건에서 이득은 3.7GHz에서 약 19dB, 잡음지수는 2.7dB를 보였으며, 35dBc의 이미지시호 제거 특성을 보였다. 저 잡음과 고 이득 특성을 갖는 캐스코드 MMIC 증폭단을 이용하여 마이크로파 수신기의 전단부의 설계가 가능함을 보였으며 이미지 제거 필터의 성능을 만족시키기 위하여 능동필터와 함께 설계할 경우 RF 수신 전단부의 완전한 MMIC 설계가 가능함을 알 수 있었다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권8호
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• pp.3103-3120
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• 2015

This paper presents a single-phase energy metering chip with built-in calibration function to measure electric power quantities. The entire chip consists of an analog front end, a filter block, a computation engine, a calibration engine, and an external interface block. The key design issues are how to reduce the implementation costs of the computation engine from repeatedly used arithmetic operations and how to simplify calibration procedure and reduce calibration time. The proposed energy metering chip simplifies the computation engine using time-division multiplexed arithmetic units. It also provides a simple and fast calibration scheme by using integrated digital calibration functionality. The chip is fabricated with 0.18-μm six-layer metal CMOS process and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4096 kHz and consumes 9.84 mW in 3.3 V supply.

• ETRI Journal
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• 제45권1호
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• pp.28-44
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• 2023

We propose short packet communication in an underlay cognitive radio network assisted by an intelligent reflecting surface (IRS) composed of multiple reconfigurable reflectors. This scheme, called the IRS protocol, operates in only one time slot (TS) using the IRS. The IRS adjusts its phases to give zero received cumulative phase at the secondary destination, thereby enhancing the end-to-end signal-to-noise ratio. The transmitting power of the secondary source is optimized to simultaneously satisfy the multi-interference constraints, hardware limitations, and performance improvement. Simulation and analysis results of the average block error rates (BLERs) show that the performance can be enhanced by installing more reconfigurable reflectors, increasing the blocklength, lowering the number of required primary receivers, or sending fewer information bits. Moreover, the proposed IRS protocol always outperforms underlay relaying protocols using two TSs for data transmission, and achieves the best average BLER at identical transmission distances between the secondary source and secondary destination. The theoretical analyses are confirmed by Monte Carlo simulations.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권9호
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• pp.2505-2528
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• 2023

The field of facial expression recognition (FER) has been actively researched to improve human-computer interaction. In recent years, deep learning techniques have gained popularity for addressing FER, with numerous studies proposing end-to-end frameworks that stack or widen significant convolutional neural network layers. While this has led to improved performance, it has also resulted in larger model sizes and longer inference times. To overcome this challenge, our work introduces a novel lightweight model architecture. The architecture incorporates three key factors: Depth-wise Separable Convolution, Residual Block, and Attention Modules. By doing so, we aim to strike a balance between model size, inference speed, and accuracy in FER tasks. Through extensive experimentation on popular benchmark FER datasets, our proposed method has demonstrated promising results. Notably, it stands out due to its substantial reduction in parameter count and faster inference time, while maintaining accuracy levels comparable to other lightweight models discussed in the existing literature.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.322-325
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• 2005

TTX(Tilting Train eXpress) is being designed for improving the speed of conventional railway. The purpose of this study is to evaluate energy absorbing capacity and driver's survivability for a design candidate of the front end structure of TTX. A FE model with honeycomb block, under frame, and body frame is generated for crash simulation. Based on a level-crossing accident scenario, numerical simulation is performed using LS-DYNA. The results of crash analysis show that strength improvement of the current front end structure design candidate is needed to ensure driver safety.

• 한국컴퓨터정보학회:학술대회논문집
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• 한국컴퓨터정보학회 2017년도 제55차 동계학술대회논문집 25권1호
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• pp.133-134
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• 2017

본 논문에서는 APT 공격의 공격 시나리오와 그에 따른 방어 시나리오를 구상하여 기존 방어법의 문제점을 찾고 방어대책을 제시하고 솔루션을 구축하였다. 제안된 방어 프로세스는 기존의 방식과 달리 END-POINT에서 침투에 대해 모니터링을 통하여 APT공격에 대응하는 방식이다. 공격 툴 넷버스, 백오리피스, 서브세븐, 스쿨버스를 이용해서 공격을 시도 한 뒤 본 논문에서 구축한 방어 프로세스를 이용하여 방어 실험을 실시하였다.