• Proceedings of the Korean Magnestics Society Conference
• /
• 2000.09a
• /
• pp.61-81
• /
• 2000

Developed two GMR memory architectures, 1R/0T for high density applications, 2R/5T for high speed applications, Embedded GMR technology shall offer rad hard community, Dynamic Reprogrammability, Rapid System Reconfigurability, Code modification in flight, Embedded GMR technology is promising for commercial applications

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.14-24
• /
• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• Journal of Internet Computing and Services
• /
• v.11 no.4
• /
• pp.95-106
• /
• 2010

Recently multiple process communicate together. They share resource and information for cooperation in complicated programming environment. Kernel provides IPC (Inter -Process Communication) for communication with each other process. Shared Memory is a technique that many processes can access to identical memory area in the Linux environment. In this paper, we propose a performance improvement method of shared memory in the dual-core embedded linux system which is consist of different core and different operating system. We construct the MPC2530F (ARM926F+ARM946E) linux system and measure the performance therein. We attempt a performance enhancement in each CPU for each process which uses a shared memory.

• The KIPS Transactions:PartA
• /
• v.12A no.3 s.93
• /
• pp.223-228
• /
• 2005

Several researchers have pointed out that the energy consumption in memory takes a dominant fraction on the energy budget of a whole embedded system. This applies to the embedded Java virtual machine tn, and to develop a more energy-efficient JVM it is absolutely necessary to optimize the energy usage in Jana memory. In this paper we have analyzed the logical memory access pattern in JVM as it executes numerous number of bytecode instructions while running a Java program. The access pattern gives us an insight how to design and select a suitable memory technology for Java memory. We present the memory access pattern for the three logical data spaces of JVM: heap, operand stack, and local variable array. The result saws that operand stack is accessed most frequently and uniformly, whereas heap used least frequently and non-uniformly among the three. Both heap and local variable array are accessed mostly in read-only fashion, but no remarkable difference is found between read and write operations for operand stack usage.

• Journal of KIISE:Computer Systems and Theory
• /
• v.36 no.2
• /
• pp.102-110
• /
• 2009

The memory wall is the growing disparity of speed between CPU and memory outside the CPU chip. An economical solution is a memory hierarchy organized into several levels, such as processor registers, cache, main memory, disk storage. We introduce a novel memory hierarchy optimization technique in Linux based embedded systems using on-chip SRAM for the first time. The optimization technique allocates On-Chip SRAM to the code/data that selected by programmers by using virtual memory systems. Experiments performed with nine applications indicate that the runtime improvements can be achieved by up to 35%, with an average of 14%, and the energy consumption can be reduced by up to 40%, with an average of 15%.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.7 no.5
• /
• pp.285-290
• /
• 2012

In this paper, we propose a fast encoding algorithm for scalable video encoding without compromising coding performance. Through analysis on multiple motion estimation processes performed at the enhancement layer, we show redundant motion estimations and suggest the condition under which the redundant ones can efficiently be determined without additional memory. Based on the condition, the redundant motion estimation processes are excluded in the proposed algorithm. Simulation results show that the proposed algorithm is faster than the conventional fast encoding method without performance degradation and additional memory.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.17 no.4
• /
• pp.217-228
• /
• 2022

Currently, there are increasing demands for applying deep neural networks (DNNs) in the embedded domain such as classification and object detection. The DNN processing in embedded domain often requires custom hardware such as NPU for acceleration due to the constraints in power, performance, and area. Processing DNN models requires a large amount of data, and its seamless transfer to NPU is crucial for performance. In this paper, we developed a cycle-accurate NPU simulator to evaluate diverse NPU microarchitectures. In addition, we propose a novel technique for reducing the number of memory accesses when processing convolutional layers in convolutional neural networks (CNNs) on the NPU. The main idea is to reuse data with memory interleaving, which recycles the overlapping data between previous and current input windows. Data memory interleaving makes it possible to quickly read consecutive data in unaligned locations. We implemented the proposed technique to the cycle-accurate NPU simulator and measured the performance with LeNet-5, VGGNet-16, and ResNet-50. The experiment shows up to 2.08x speedup in processing one convolutional layer, compared to the baseline.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.12
• /
• pp.54-60
• /
• 2007

This paper proposes a built-in-self-repair (BISR) structure using 2-dimensional spare memory to effectively self-repair faults of an embedded memory. In case of multiple faults in the same row (column) of an embedded memory, the previous method using 1-D spare column (row) memory needs the same number of spare memory columns (rows) as the number of faults to self-repair them. while the new method using 2-D spare memory needs only one spare row (column) to self-repair them. Also, the virtual divided memory is adopted to be able to self-repair using not a full spare column memory but the only partial spare column memory corresponding to the faults. A self-repair circuit with $64\times1-bit$ core memory and $2\times8$ 2-D spare memory is designed. And the circuit includes a built-in-self-test block using the 13N March algorithm. The circuit has been implemented using the $0.25{\mu}m$ MagnaChip CMOS process and has $1.1\times0.7mm^2$ chip area with 10,658 transistors.

• Journal of the Korea Society of Computer and Information
• /
• v.22 no.5
• /
• pp.11-19
• /
• 2017

In this paper, we propose a hypervisor for embedded systems based on ARM microprocessor. The proposed hypervisor makes it possible to run several real-time kernels concurrently on a single embedded system by virtualizing its microprocessor. With assistance of MMU, it supports virtual memory which enables each guest operating system has its own address space. Exploiting the fact that most embedded systems use memory-mapped I/O device, it provides a mechanism to distribute an external interrupt to virtual machines properly. It also achieves load balancing through live migration which moves a running virtual machine to other embedded system. Unlike other para-virtualization techniques, minor modifications are needed to run it on the hypervisor. Extensive performance measurement studies are conducted to show that the proposed hypervisor has enough potentiality of its real-world application.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.12 no.3
• /
• pp.177-184
• /
• 2017

High performance non-volatile memory system can mitigate the gap between main memory and storage. However, no single memory devices fulfill the requirements. Non-volatile Dual In-line Memory Module (NVDIMM) consisted of DRAMs and NAND Flashes has been proposed to achieve the performance and non-volatility simultaneously. When power outage occurs, data in DRAM is backed up into NAND Flash using a small-size external energy storage such as a supercapacitor. Backup and restore operations of NVDIMM do not cooperate with the operating system in the NVDIMM standard, thus there is room to optimize its operation. This paper analysis the operation of NVDIMM and proposes a method to reduce backup and restore time. Particularly, data compression is introduced to reduce the amount of data that to be backed up and restored. The simulation results show that the proposed method reduces up to 72.6% of backup and restore time.