• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.182-192
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• 2010

This paper proposes the hardware IP design of JBIG2 encoder. In order to facilitate the next generation FAX after the standardization of JBIG2, major modules of JBIG2 encoder are designed and implemented, such as symbol extraction module, Huffman coder, MMR coder, and MQ coder. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the synthesis of VHDL code. To minimize the memory usage, 128 lines of input image are processed succesively instead of total image. The synthesized IPs are downloaded to Virtex-4 FX60 FPGA on ML410 development board. The four synthesized IPs utilize 36.7% of total slice of FPGA. Using Active-HDL tool, the generated IPs were verified showing normal operation. Compared with the software operation using microblaze cpu on ML410 board, the synthesized IPs are better in operation time. The improvement ratio of operation time between the synthesized IP and software is 17 times in case of symbol extraction IP, and 10 times in Huffman coder IP. MMR coder IP shows 6 times faster and MQ coder IP shows 2.2 times faster than software only operation. The synthesized H/W IP and S/W module cooperated to succeed in compressing the CCITT standard document.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.4
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• pp.17-22
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• 2012

Convolution filtering methods have been widely applied to various digital signal processing fields for image blurring, sharpening, edge detection, and noise reduction, etc. According to their application purpose, the filter mask size or shape and the mask value are selected in advance, and the designed filter is applied to input image for the convolution processing. In this paper, we proposed an image processing acceleration method for the convolution processing by using two-dimensional Look-up table (LUT) and overlap-region buffering technique. First, based on the fixed convolution mask value, the multiplication operation between 8 or 10 bit pixel values of the input image and the filter mask values is performed a priori, and the results memorized in LUT are referred during the convolution process. Second, based on symmetric structural characteristics of the convolution filters, inherent duplicated operation region is analysed, and the saved operation results in one step before in the predefined memory buffer is recalled and reused in current operation step. Through this buffering, unnecessary repeated filter operation on the same regions is minimized in sequential manner. As the proposed algorithms minimize the computational amount needed for the convolution operation, they work well under the operation environments utilizing embedded systems with limited computational resources or the environments of utilizing general personnel computers. A series of experiments under various situations verifies the effectiveness and usefulness of the proposed methods.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.3
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• pp.191-198
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• 2009

The FAT (File Allocation Table) compatible file system has been widely used in mobile devices and memory cards because of its data exchangeability among numerous platforms recognizing the FAT file system. By the way. modern embedded systems have tough demands for instant power failure recovery and superior performance for multimedia applications. The key issue is how to achieve the goals of superior write performance and instant booting capability while controlling compatibility issues. To achieve the goals while controlling compatibility issues. we devised a temporary meta-data journaling scheme for a FAT compatible file system. Benchmark results of the scheme implemented in a FAT compatible file system shows that it really improves write performance of the FAT file system by converting small random write for meta-data update to a large sequential write in journaling area. Also, it provides natural way to implement the instant booting capability. Nevertheless, the file system compatibility is temporarily compromised by the scheme because it stores updated meta-data in the temporary journaling area rather than to their original locations. However, the compatibility can be fully recovered at any time by journal-flushing that copies meta-data in journaling area to their original locations. Generally, the journal-flushing is done before un-mounting a memory card so that it can be used in other mobile devices which recognized FAT file system but not the temporary meta-data journaling scheme.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.4
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• pp.232-243
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• 2002

There are many methods for improving TLB (translation lookaside buffer) performance, such as increasing the number of entry in TLB, supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. So, we propose the new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub-fully associative TLBs. These two banked-TLB structures are integrated into a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also power consumption can be reduced by around 50% comparing with the fully associative TLB.

• Journal of Internet Computing and Services
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• v.22 no.2
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• pp.59-68
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• 2021

As artificial intelligence(AI) technologies, which have made rapid growth recently, began to be applied to the marine environment such as ships, there have been active researches on the application of CNN-based models specialized for digital videos. In E-Navigation service, which is combined with various technologies to detect floating objects of clash risk to reduce human errors and prevent fires inside ships, real-time processing is of huge importance. More functions added, however, mean a need for high-performance processes, which raises prices and poses a cost burden on shipowners. This study thus set out to propose a method capable of processing information at a high rate while maintaining the accuracy by applying Quantization techniques of a deep learning model. First, videos were pre-processed fit for the detection of floating matters in the sea to ensure the efficient transmission of video data to the deep learning entry. Secondly, the quantization technique, one of lightweight techniques for a deep learning model, was applied to reduce the usage rate of memory and increase the processing speed. Finally, the proposed deep learning model to which video pre-processing and quantization were applied was applied to various embedded boards to measure its accuracy and processing speed and test its performance. The proposed method was able to reduce the usage of memory capacity four times and improve the processing speed about four to five times while maintaining the old accuracy of recognition.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.5
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• pp.467-474
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• 2019

In this paper, we propose a novel method to improve FPS while maintaining the accuracy of YOLO v2 model in NVIDIA Jetson TX1. In general, in order to reduce the amount of computation, a conversion to an integer operation or reducing the depth of a network have been used. However, the accuracy of recognition can be deteriorated. So, we use methods to reduce computation and memory consumption through adjustment of the filter size and integrated computation of the network The first method is to replace the $3{\times}3$ filter with a $1{\times}1$ filter, which reduces the number of parameters to one-ninth. The second method is to reduce the amount of computation through CBR (Convolution-Add Bias-Relu) among the inference acceleration functions of TensorRT, and the last method is to reduce memory consumption by integrating repeated layers using TensorRT. For the simulation results, although the accuracy is decreased by 1% compared to the existing YOLO v2 model, the FPS has been improved from the existing 3.9 FPS to 11 FPS.

• The KIPS Transactions:PartC
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• v.10C no.5
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• pp.585-594
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• 2003

Java card is one of promising smart card platform with java technology. Java card defines necessary packages and classes for Embedded device that have small memory such as smart card Jana card is compatible with EMV that is Industry specification standard and ISO-7816 that is international standard. However, Java card is not offers user authentication protocol. In this paper, We design and implement an user authentication protocol applicable wireless devices based on Java Card using standard 3GPP Specification (SMS), Java Card Specification (APDU), Cryptography and so on. Our Java Card user authentication techniques can possibly be applied to the area of M-Commerce, Wireless Security, E-Payment System, Mobile Internet, Global Position Service, Ubiquitous Computing and so on.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.10
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• pp.213-220
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• 2020

The power consumption and performance of hardware-based mobile and IoT embedded systems that require high specifications are one of the important issues of these systems. In particular, the problem of excessive power consumption is because it causes a problem of increasing heat generation and shortening the life of the device. In addition, in the same environment, software also needs to perform stable operation in limited power and memory, thereby increasing power consumption of the device. In order to solve these issues, we propose a Low level power improvement via identifying performance dissipation. The proposed method identifies complex modules (especially Cyclomatic complexity, Coupling & Cohesion) through code visualization, and helps to simplify low power code patterning and performance code. Therefore, through this method, it is possible to optimize the quality of the code by reducing power consumption and improving performance.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.1
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• pp.25-32
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• 2004

Nowadays image processing is very useful for some field of traffic applications. The one reason is we can construct the system in a low price, the other is the improvement of hardware processing power, it can be more fast to processing the data. In traffic field, the development of image using system is interesting issue. Because it has the advantage of price of installation and it does not obstruct traffic during the installation. In this study, 1 propose the traffic monitoring system that implement on the embedded system environment. The whole system consists of two main part, one is host controller board, the other is image processing board. The part of host controller board take charge of control the total system interface of external environment, and OSD(On screen display). The part of image processing board takes charge of image input and output using video encoder and decoder, Image classification and memory control of using FPGA, control of mouse signal. And finally, for stable operation of host controller board, uC/OS-II operating system is ported on the board.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.221-221
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• 2013

Striving to replace the well known silicon nanocrystals embedded in oxides with solution-processable charge-trapping materials has been debated because of large scale and cost effective demands. Herein, a silicon quantum dot-polystyrene nanocomposite (SiQD-PS NC) was synthesized by postfunctionalization of hydrogen-terminated silicon quantum dots (H-SiQDs) with styrene using a thermally induced surface-initiated polymerization approach. The NC contains two miscible components: PS and SiQD@PS, which respectively are polystyrene and polystyrene chains-capped SiQDs. Spin-coated films of the nanocomposite on various substrate were thermally annealed at different temperatures and subsequently used to construct metal-insulator-semiconductor (MIS) devices and thin film field effect transistors (TFTs) having a structure p-$S^{++}$/$SiO_2$/NC/pentacene/Au source-drain. C-V curves obtained from the MIS devices exhibit a well-defined counterclockwise hysteresis with negative fat band shifts, which was stable over a wide range of curing temperature ($50{\sim}250^{\circ}C$. The positive charge trapping capability of the NC originates from the spherical potential well structure of the SiQD@PS component while the strong chemical bonding between SiQDs and polystyrene chains accounts for the thermal stability of the charge trapping property. The transfer curve of the transistor was controllably shifted to the negative direction by chaining applied gate voltage. Thereby, this newly synthesized and solution processable SiQD-PS nanocomposite is applicable as charge trapping materials for TFT based memory devices.